Rtc Second/1Hz Register - Epson S1C17M01 Technical Manual

Note: The counter value may not be read correctly while the stopwatch counter is running. The
RTCSWCTL.BCD10[3:0]/BCD100[3:0] bits must be read twice and assume the counter
value was read successfully if the two read results are the same.
Bits 7–5 Reserved
Bit 4 SWRST
This bit resets the stopwatch counter to 0x00.
1 (W): Reset
0 (W): Ineffective
0 (R): Always 0 when being read
When the stopwatch counter in running status is reset, it continues counting from count 0x00. The
stopwatch counter retains 0x00 if it is reset in idle status.
Bits 3–1 Reserved
Bit 0 SWRUN
This bit starts/stops the stopwatch counter.
1 (R/W): Running/start control
0 (R/W): Idle/stop control
When the stopwatch counter stops counting by writing 0 to this bit, the counter retains the value when
it stopped. Writing 1 to this bit again resumes counting from the value retained.
Note: The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the
RTCSWCTL.SWRUN bit. Therefore, the counter value may be incremented (+1) from the
value at writing 0.

RTC Second/1Hz Register

Register name Bit
RTCSEC 15
14–12 RTCSH[2:0]
11–8 RTCSL[3:0]
7
6
5
4
3
2
1
0
Bit 15 Reserved
Bits 14–12 RTCSH[2:0]
Bits 11–8 RTCSL[3:0]
The RTCSEC.RTCSH[2:0] bits and the RTCSEC.RTCSL[3:0] bits are used to set and read the 10-sec-
ond digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD
code within the range from 0 to 59.
Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL.
RTCBSY bit = 1.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
– 0
0x0
0x0
RTC1HZ 0
RTC2HZ 0
RTC4HZ 0
RTC8HZ 0
RTC16HZ 0
RTC32HZ 0
RTC64HZ 0
RTC128HZ 0
Seiko Epson Corporation
8 REAL-TIME CLOCK (RTCA)
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R Cleared by setting the
RTCCTL.RTCRST bit to 1.
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
Remarks
8-9