Vector Table Base Address (Ttbr) - Epson S1C17M01 Technical Manual

5 INTERRUPT CONTROLLER (ITC)
Vector number/
Software interrupt Vector address
number
4 (0x04) TTBR + 0x10
5 (0x05) TTBR + 0x14
6 (0x06) TTBR + 0x18
7 (0x07) TTBR + 0x1c
8 (0x08) TTBR + 0x20
9 (0x09) TTBR + 0x24
10 (0x0a) TTBR + 0x28
11 (0x0b) TTBR + 0x2c
12 (0x0c) TTBR + 0x30
13 (0x0d) TTBR + 0x34
14 (0x0e) TTBR + 0x38
15 (0x0f) TTBR + 0x3c
16 (0x10) TTBR + 0x40
17 (0x11) TTBR + 0x44
18 (0x12) TTBR + 0x48
19 (0x13) TTBR + 0x4c
20 (0x14) TTBR + 0x50
: :
31 (0x1f) TTBR + 0x7c
*1 When the same interrupt level is set

5.2.1 Vector Table Base Address (TTBR)

The MSCTTBRL and MSCTTBRH registers are provided to set the base (start) address of the vector table in which
interrupt vectors are programmed. "TTBR" described in Table 5.2.1 means the value set to these registers. After an
initial reset, the MSCTTBRL and MSCTTBRH registers are set to address 0x8000. Therefore, even when the vec-
tor table location is changed, it is necessary that at least the reset vector be written to the above address. Bits 7 to 0
in the MSCTTBRL register are fixed at 0, so the vector table always begins from a 256-byte boundary address.
5-2
Hardware interrupt name
Supply voltage detector Low power supply voltage detection
interrupt
Port interrupt Port input
Clock generator interrupt • IOSC oscillation stabilization waiting completion
• OSC1 oscillation stabilization waiting completion
• OSC1 oscillation stop
• IOSC oscillation auto-trimming completion
Real-time clock interrupt • 1-day, 1-hour, 1-minute, and 1-second
• 1/32-second, 1/8-second, 1/4-second, and 1/2-second
• Stopwatch 1 Hz, 10 Hz, and 100 Hz
• Alarm
• Theoretical regulation completion
16-bit timer Ch.0 interrupt Underflow
UART interrupt • End of transmission
• Framing error
• Parity error
• Overrun error
• Receive buffer two bytes full
• Receive buffer one byte full
• Transmit buffer empty
16-bit timer Ch.1 interrupt Underflow
Synchronous serial interface • End of transmission
Ch.0 interrupt • Receive buffer full
• Transmit buffer empty
• Overrun error
I 2 C interrupt • End of data transfer
• General call address reception
• NACK reception
• STOP condition
• START condition
• Error detection
• Receive buffer full
• Transmit buffer empty
16-bit timer Ch.2 interrupt Underflow
16-bit timer Ch.3 interrupt Underflow
16-bit timer Ch.4 interrupt Underflow
Synchronous serial interface • End of transmission
Ch.1 interrupt • Receive buffer full
• Transmit buffer empty
• Overrun error
LCD driver interrupt Frame
R/F converter interrupt • Reference oscillation completion
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
MR sensor controller • Unit counter compare match
interrupt • Event counter Ch.0/1/2 underflow
• Comparator Ch.0/1 change
• Phase dropout
• Stop
• Reverse rotation
• Normal rotation
reserved
:
reserved
Seiko Epson Corporation
Hardware interrupt flag
–
:
–
S1C17M01 TECHNICAL MANUAL
Priority
High *1
↑
↓
Low
*1
(Rev. 1.2)