Epson S1C17M01 Technical Manual page 238

REVISION HISTORY
Code No. Page
412361701 7-2 WDT: During SLEEP mode
(Old) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is
(New) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is
7-3 WDT: WDT Control Register
Modified the register table (NMIXRST, STATNMI → Reserved)
WDT: WDT Control Register
(Old) Bits 15–10 Reserved
(New) Bits 15–5 Reserved
7-4 WDT: WDT Control Register - Bits 3–0 WDTRUN[3:0]
(Old) Since an NMI or reset may be generated immediately after running depending on the counter
(New) Since a reset may be generated immediately after running depending on the counter value, WDT
9-3 SVD: Starting detection
(Old) 3. Set the following SVDCTL register bits:
(New) 3. Set the following SVDCTL register bits:
Reading detection results
(Old) • Power supply voltage (V
(New) • Power supply voltage (V
9-5 SVD: SVD Interrupt
(Old) Once the SVDINTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subse-
(New) Once the SVDINTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subse-
9-6 SVD: SVD Control Register - Bits 12–8 SVDC[4:0]
(Old) These bits select a comparison voltage for detecting low voltage from among 20 levels.
(New) These bits select an SVD detection voltage V
9-7 SVD: SVD Status and Interrupt Flag Register - Bit 8 SVDDT
(Old) 1 (R): Power supply voltage (V
(New) 1 (R): Power supply voltage (V
9-8 SVD: SVD Interrupt Enable Register - Bit 0 SVDIE
(Old) Notes: ...
(New) Notes: ...
cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI
or reset handler is executed. ...
If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary
NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction.
cleared by a reset if it continues for more than the reset generation cycle and the reset handler is
executed. ...
If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary
reset after clearing SLEEP mode, reset WDT before executing the slp instruction.
Bit 9 N MIXRST
...
Bit 8 STATNMI
...
Bits 7–5 Reserved
value, WDT should also be reset concurrently when running WDT.
should also be reset concurrently when running WDT.
...
- SVDCTL.SVDC[4:0] bits (Set comparison voltage)
...
- VDCTL.SVDC[4:0] bits (Set SVD detection voltage V
DD
• Power supply voltage (V
DD
... After the SVDCTL.SVDC[4:0] bits setting value is altered to change the comparison voltage
when the SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the
SVDINTF.SVDDT bit ...
DD
• Power supply voltage (V
DD
... After the SVDCTL.SVDC[4:0] bits setting value is altered to change the SVD detection voltage
V when the SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading
SVD
the SVDINTF.SVDDT bit ...
quently returns to a value exceeding the comparison voltage value.
quently returns to a value exceeding the SVD detection voltage V
Table 9.6.3 Comparison Voltage Setting
SVDCTL.SVDC[4:0] bits | Comparison voltage [V]
Table 9.6.3 Setting of SVD Detection Voltage V
SVDCTL.SVDC[4:0] bits | SVD detection voltage V
0 (R): Power supply voltage (V
0 (R): Power supply voltage (V
• To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before
enabling interrupts.
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
Contents
)
SVD
or EXSVD) ≥ Comparison voltage when SVDINTF.SVDDT bit = 0
or EXSVD) < Comparison voltage when SVDINTF.SVDDT bit = 1
or EXSVD) ≥ SVD detection voltage V
or EXSVD) < SVD detection voltage V
for detecting low voltage from among 20 levels.
SVD
SVD
[V]
SVD
or EXSVD) < comparison voltage
DD
or EXSVD) ≥ comparison voltage
DD
or EXSVD) < SVD detection voltage V
DD
or EXSVD) ≥ SVD detection voltage V
DD
when SVDINTF.SVDDT bit = 0
SVD
when SVDINTF.SVDDT bit = 1
SVD
.
SVD
SVD
SVD