Control Registers; Amrc Clock Control Register; Amrc Afe Control Register - Epson S1C17M01 Technical Manual

16 MR SENSOR CONTROLLER (AMRC)

16.6 Control Registers

Note: When writing to the control registers, do not alter the "(reserved)" bits from the "Initial" value.

AMRC Clock Control Register

Register name Bit
AMRCCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the AMRC operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits indicate the division ratio of the AMRC operating clock. It is fixed at 0x0 (divided by 1).
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits indicate the clock source of the AMRC. It is fixed at 0x1 (OSC1).

AMRC AFE Control Register

Register name Bit
AMRCACTL 15
14–8 –
7–6 (reserved)
5–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 EXHYS1INV
Bit 2 EXHYS0INV
These bits invert the external hysteresis polarity.
1 (R/W): External hysteresis polarity is inverted.
0 (R/W): External hysteresis polarity is not inverted.
The following shows the correspondence between the bit and external hysteresis:
AMRCACTL.EXHYS1INV bit: External hysteresis 1 (CMPIN1P pin)
AMRCACTL.EXHYS0INV bit: External hysteresis 0 (CMPIN0P pin)
Bit 1 HYS1EN
Bit 0 HYS0EN
These bits enable the internal hysteresis.
1 (R/W): Enable internal hysteresis
0 (R/W): Disable internal hysteresis
16-8
Bit name Initial
0x00
DBRUN 1
0x0
0x0
0x0
0x1
Bit name Initial
(reserved) 0
0x00
0x0
0x0
EXHYS1INV 0
EXHYS0INV 0
HYS1EN 1
HYS0EN 1
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R
– R
H0 R
Reset R/W
H0 R/W –
– R
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
S1C17M01 TECHNICAL MANUAL
Remarks
Remarks
(Rev. 1.2)