Epson S1C17M01 Technical Manual page 239

Code No. Page
412361701 10-1 T16: Figure 10.1.1 Configuration of a T16 Channel
Modified the figure (The I/O port (chattering filter) was deleted.)
T16: Input Pin
(Old) If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be
(New) If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be
10-6 T16: T16 Ch.n Reload Data Register
(Old) Note: The T16_nTR register cannot be altered while the timer is running (T16_nCTL.PRUN bit = 1),
(New) Notes: • The T16_nTR register cannot be altered while the timer is running (T16_nCTL.PRUN bit = 1),
10-7 T16: T16 Ch.n Interrupt Enable Register - Bit 0 UFIE
(Old) Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before
(New) Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
13-14 I2C: Figure 13.4.7.1 Example of Data Transfer Starting Operations in 10-bit Address Mode (Slave Mode)
(Old) Operations by I2C (master mode)
(New) Operations by the external master
AP-A-3 List of Peripheral Circuit Control Registers: WDT Control Register
Modified the register table (NMIXRST, STATNMI → Reserved)
AP-C-1 Mounting Precautions: V
(Old) No description
(New) If fluctuations in the Flash programming voltage V
412361702 1-2 1.1 Features
Modified Table 1.1.
Shipping form: A JEITA name was added to the package name.
2-6 2.3.4 Operations
Oscillation start time and oscillation stabilization waiting time
Oscillation stabilization waiting time for the IOSC oscillator circuit → 16 IOSCCLK clocks
Added the following description:
The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16,384 OSC1CLK
clocks or more.
3-3 3.3.3 List of debugger input/output pins
Added notes.
Notes: • Do not drive the DCLK pin with a high level from outside (e.g. pulling up with a resistor). Also,
4-3 4.3.3 Flash Programming
Modified Figure 4.3.3.1.
C
Added the following description:
When supplying the V
6-16 6.7.7 Pd Port Group
Modified Table 6.7.7.1.
PDIOEN register: PDOEN[1:0] → PDOEN[2:0]
7-4 7.4 Control Registers
WDT Control Register
Corrected the description of the WDTRUN[3:0] bit.
Bits 3–0 WDTRUN[3:0]
assigned to the port before using the event counter function. The EXCLm signal can be input
through the chattering filter. For more information, refer to the "I/O Ports" chapter.
assigned to the port before using the event counter function. For more information, refer to the "I/O
Ports" chapter.
as an incorrect initial value may be preset to the counter.
as an incorrect initial value may be preset to the counter.
• When one-shot mode is set, the T16_nTR.TR[15:0] bits should be set to a value equal to
or greater than 0x0001.
enabling interrupts.
cleared before enabling interrupts.
pin
PP
V and V pins to suppress fluctuations within V
SS PP
the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens
PP
of mA to flow.
Added a figure (V pin connection example)
PP
do not connect (short-circuit) between the DCLK pin and another GPIO port. In the both cases,
the IC may not start up normally due to unstable pin input/output status at power on.
• Do not drive the DSIO pin with a low level from outside, as it generates a debug interrupt that
puts the CPU into DEBUG mode.
was added.
VPP
power source, be sure to connect C
PP
These bits control WDT to run and stop.
0xa (WP):
Values other than 0xa (WP): Run
0xa (R):
0x0 (R):
Contents
Operations by the external slave
Operations by I2C (slave mode)
is large, connect a capacitor C
PP
± 1 V. The C
PP
VPP
Stop
Idle
Running
REVISION HISTORY
between the
VPP
should be placed as close to
VPP
for stabilizing the V voltage.
PP