Lcd8A Timing Control Register; Lcd8A Power Control Register - Epson S1C17M01 Technical Manual

LCD8A Timing Control Register

Register name Bit
LCD8TIM 15–14 –
13–12 BSTC[1:0]
11
10–8 NLINE[2:0]
7–4 FRMCNT[3:0]
3
2–0 LDUTY[2:0]
Bits 15–14 Reserved
Bits 13–12 BSTC[1:0]
These bits select the booster clock frequency for the LCD voltage booster.
f
CLK_LCD8A
Bit 11 Reserved
Bits 10–8 NLINE[2:0]
These bits enable the n-line inverse AC drive function and set the number of inverse lines. For more
information, refer to "n-Segment-Line Inverse AC Drive."
Bits 7–4 FRMCNT[3:0]
These bits set the frame frequency. For more information, refer to "Frame Frequency."
Bit 3 Reserved
Bits 2–0 LDUTY[2:0]
These bits set the drive duty. For more information, refer to "Drive Duty Switching."

LCD8A Power Control Register

Register name Bit
LCD8PWR 15–12 LC[3:0]
11–9 –
8
7–3 –
2
1
0
Bits 15–12 LC[3:0]
These bits set the LCD panel contrast.
Bits 11–9 Reserved
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x0
0x1
– 0
0x0
0x3
– 0
0x7
Table 14.8.2 Booster Clock Frequency
LCD8TIM.BSTC[1:0] bits
0x3
0x2
0x1
0x0
: LCD8A operating clock frequency [Hz]
Bit name Initial
0x0
0x0
BSTEN 0
0x00
HVLD 0
VCSEL 0
VCEN 0
Table 14.8.3 LCD Contrast Adjustment
LCD8PWR.LC[3:0] bits
0xf
0xe
:
0x1
0x0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R/W
H0 R/W
– R
H0 R/W
Booster clock frequency [Hz]
f /64
CLK_LCD8A
f /32
CLK_LCD8A
f /16
CLK_LCD8A
f /4
CLK_LCD8A
Reset R/W
H0 R/W –
– R
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
Contrast
High (dark)
↑
:
↓
Low (light)
14 LCD DRIVER (LCD8A)
Remarks
Remarks
14-13