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Bit 4
EPOUTTRG
This bit issues a software trigger to output a pulse.
1 (W):
Output trigger
0 (W):
Ineffective
1 (R):
Output initiating
0 (R):
Output initiating operations finished
Bits 3–0
TRGCYC[3:0]
These bits set the measurement trigger cycle.
Setting value
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
The order of 16 Hz (low-rev trigger) should be selected while the magnet is at stop status to reduce
power consumption, and switch it to the order of 1,024 Hz (high-rev trigger) after the magnet starts
rotation.
AMRC Normal Rotation Counter Register
Register name
Bit
AMRCNMLCNT
15–0 NMLCNT[15:0]
Bits 15–0 NMLCNT[15:0]
The normal rotation counter value can be read out from these bits.
The correct value may not be read during counting. The AMRCNMLCNT register must be read twice
and assume the counter value was read successfully if the two read results are the same. For more in-
formation on the normal rotation counter, refer to the "Measurement Control and Operations" section.
AMRC Reverse/Stop Counter Register
Register name
Bit
AMRCREVSTPCNT 15–0 REVSTPCNT[15:0]
Bits 15–0 REVSTPCNT[15:0]
The reverse/stop counter value can be read out from these bits.
The correct value may not be read during counting. The AMRCREVSTPCNT register must be read
twice and assume the counter value was read successfully if the two read results are the same. For more
information on the reverse/stop counter, refer to the "Measurement Control and Operations" section.
AMRC Event Counter Ch.x Register
Register name
Bit
AMRCECNTx
15–8 ECNT[7:0]
7–0 ECPR[7:0]
Bits 15–8 ECNT[7:0]
The event counter Ch.x (x = 0 to 2) value can be read out from these bits.
The correct value may not be read during counting. The AMRCECNTx.ECNT[7:0] bits must be read
twice and assume the counter value was read successfully if the two read results are the same. For
more information on the event counter, refer to "Measurement Control and Operations."
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Table 16.6.1 Measurement Trigger Cycle Settings
Trigger cycle [Hz]
1,365.3
682.7
341.3
4,096
2,048
1,024 (high-rev trigger)
512
256
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Bit name
Initial
0xff
0xff
Seiko Epson Corporation
16 MR SENSOR CONTROLLER (AMRC)
Setting value
Trigger cycle [Hz]
0x7
128
0x6
64
0x5
32
0x4
16 (low-rev trigger)
0x3
8
0x2
4
0x1
2
0x0
1
Reset
R/W
–
R
Cleared by writing 1 to the
AMRCCTL.RSTUPCNT bit.
Reset
R/W
–
R
Cleared by writing 1 to the
AMRCCTL.RSTUPCNT bit.
Reset
R/W
H0
R
–
H0
R/W
Remarks
Remarks
Remarks
16-11
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