P5 Port Group - Epson S1C17M01 Technical Manual

6.7.6 P5 Port Group

The P56 and P57 ports in the P5 port group support the GPIO and interrupt functions. The P50–P55 ports do not
support the GPIO function.
Register name Bit
P5DAT 15–14 P5OUT[7:6]
(P5 Port Data
13–8 –
Register)
7–6 P5IN[7:6]
5–0 –
P5IOEN 15–14 P5IEN[7:6]
(P5 Port Enable
13–8 –
Register)
7–6 P5OEN[7:6]
5–0 –
P5RCTL 15–14 P5PDPU[7:6]
(P5 Port Pull-up/
13–8 –
down Control Regis-
7–6 P5REN[7:6]
ter)
5–0 –
P5INTF 15–8 –
(P5 Port Interrupt
7–6 P5IF[7:6]
Flag Register)
5–0 –
P5INTCTL 15–14 P5EDGE[7:6]
(P5 Port Interrupt
13–8 –
Control Register)
7–6 P5IE[7:6]
5–0 –
P5CHATEN 15–8 –
(P5 Port Chattering
7–6 P5CHATEN[7:6]
Filter Enable
5–0 –
Register)
P5MODSEL 15–8 –
(P5 Port Mode Select
7–0 P5SEL[7:0]
Register)
P5FNCSEL 15–14 P57MUX[1:0]
(P5 Port Function
13–12 P56MUX[1:0]
Select Register)
11–10 P55MUX[1:0]
9–8 P54MUX[1:0]
7–6 P53MUX[1:0]
5–4 P52MUX[1:0]
3–2 P51MUX[1:0]
1–0 P50MUX[1:0]
P5SELy = 0
Port name
GPIO
Peripheral
P50 –
P51 –
P52 –
P53 –
P54 –
P55 –
P56 P56
P57 P57
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Table 6.7.6.1 Control Registers for P5 Port Group
Bit name Initial
0x0
0x00
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x00
0x0
0x00
0x00
0x00
0x2
0x2
0x3
0x3
0x3
0x3
0x3
0x3
Table 6.7.6.2 P5 Port Group Function Assignment
P5yMUX = 0x0 P5yMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
Seiko Epson Corporation
Reset R/W
H0 R/W –
– R
x H0 R
– R
H0 R/W –
– R
H0 R/W
– R
H0 R/W –
– R
H0 R/W
– R
– R –
H0 R/W Cleared by writing 1.
– R –
H0 R/W –
– R
H0 R/W
– R
– R –
H0 R/W
– R
– R –
H0 R/W
H0 R –
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
P5SELy = 1
P5yMUX = 0x2
(Function 2)
Pin Peripheral
– –
– –
– –
– –
– –
– –
– –
– –
6 I/O PORTS (PPORT)
Remarks
P5yMUX = 0x3
(Function 3)
Pin Peripheral Pin
– LCD8A SEG30/COM5
– LCD8A SEG31/COM4
– LCD8A COM3
– LCD8A COM2
– LCD8A COM1
– LCD8A COM0
– – –
– – –
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