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14 LCD DRIVER (LCD8A)
14.5.2 Display On/Off
The LCD display state is controlled using the LCD8DSP.DSPC[1:0] bits.
When "Display off" is selected, the drive voltage supply stops and the LCD driver pin outputs are all set to V
level.
Since "All on" and "All off" directly control the driving waveform output by the LCD driver, data in the display
data RAM is not altered. The common pins are set to dynamic drive for "All on" and to static drive for "All off."
This function can be used to make the display flash on and off without altering the display memory.
Note: When "Display off" is selected, the electric charges of V
lowing procedure.
<When the LCD drive voltages are generated in internal generation mode>
1. Set the LCD8DSP.DSPC[1:0] bit to 0x0.
2. Wait until the electric charge of the LCD panel is discharged.
3. Set the LCD8PWR.VCEN bit to 0.
4. Set the LCD8PWR.HVLD bit to 1.
5. Before stopping CLK_LCD8A, make certain that the V
1 V or less.
<When the LCD drive voltages are generated in an external generation mode>
1. Set the LCD8DSP.DSPC[1:0] bit to 0x0.
2. Wait until the electric charge of the LCD panel is discharged.
3. Turn the external power supply off.
4. Set the LCD8PWR.HVLD bit to 1.
5. Before stopping CLK_LCD8A, make certain that the V
1 V or less.
To turn the display on again, perform the above procedure in the reverse order.
14.5.3 Inverted Display
The LCD panel display can be inverted (black/white inversion) using merely control bit manipulation, without rewrit-
ing the display data RAM. Setting the LCD8DSP.DSPREV bit to 0 inverts the display; setting it to 1 returns the dis-
play to normal status. Note that the display will not be inverted when the LCD8DSP.DSPC[1:0] bits = 0x3 (All off).
14.5.4 Drive Duty Switching
Drive duty can be set to 1/8 to 1/2 or static drive using the LCD8TIM.LDUTY[2:0] bits. Table 14.5.4.1 shows the
correspondence between the LCD8TIM.LDUTY[2:0] bit settings, drive duty, and maximum number of display seg-
ments.
LCD8TIM.LDUTY[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
14-6
Table 14.5.2.1 LCD Display Control
LCD8DSP.DSPC[1:0] bits
0x3
0x2
0x1
0x0
Table 14.5.4.1 Drive Duty Settings
Duty
Valid COM pins
1/8
COM0 to COM7
1/7
COM0 to COM6
1/6
COM0 to COM5
1/5
COM0 to COM4
1/4
COM0 to COM3
1/3
COM0 to COM2
1/2
COM0 to COM1
Static
Seiko Epson Corporation
LCD display
All off (static drive)
All on
Normal display
Display off
(or V
) must be discharged in the fol-
C4
C3
(Display off)
(Disable LCD voltage regulator)
(Enable heavy load protection mode)
(or V
) voltage has dropped to V
C4
C3
(Display off)
(Enable heavy load protection mode)
(or V
) voltage has dropped to V
C4
C3
Valid SEG pins
SEG0 to SEG27
SEG0 to SEG27
SEG0 to SEG27
SEG0 to SEG27
SEG0 to SEG31
SEG0 to SEG31
SEG0 to SEG31
COM0
SEG0 to SEG31
DD
Max. number of
display segments
224 segments
196 segments
168 segments
140 segments
128 segments
96 segments
64 segments
32 segments
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
SS
-
-
DD
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