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4.4
Prescalers
The H8/3937 Series and 3937R Series are equipped with two on-chip prescalers having different
input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock
(ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral
modules. Prescaler W is a 5-bit counter using a 38.4 kHz or 80 kHz signal, obtained by dividing a
76.8 kHz or 160 kHz signal by 2, further divided by 4 (ø
/4) as its input clock. Its prescaled
w
outputs are used for timer A time-base operations.
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI1, SCI31, SC32,
the A/D converter, and the watchdog timer. The divider ratio can be set separately for each on-
chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is øosc/16, øosc/32, øosc/64, or
øosc/128.
2. Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 38.4 kHz or 80 kHz signal, obtained by dividing a 76.8 kHz
or 160 kHz signal by 2, further divided by 4 (ø
/4) as its input clock.
w
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins DX1 and DX2.
Prescaler W can be reset by setting 1 in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base.
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