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• Simultaneous transmit/receive
Figure 10-17 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
Read bit TDRE
1
in SSR
TDRE = 1?
Write transmit
data to TDR
Read bit OER
in SSR
OER = 1?
Read bit RDRF
2
in SSR
RDRF = 1?
Read receive data
in RDR
Continue data
3
transmission/reception?
Clear bits TE and
RE to 0 in SCR3
End
Figure 10-17 Example of Simultaneous Data Transmission/Reception Flowchart
300
No
Yes
Yes
No
No
Yes
Overrun error
4
processing
Yes
Notes: 1. When switching from transmission to simultaneous
transmission/reception, check that SCI3 has finished transmitting and
No
that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set
bits TE and RE to 1.
2. When switching from reception to simultaneous transmission/reception,
check that SCI3 has finished receiving, clear bit RE to 0, then check
that bit RDRF and the error flags (OER, FER, and PER) are cleared to
0, and finally set bits TE and RE to 1.
(Synchronous Mode)
1.
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
2.
Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
3.
When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
4.
If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmis-
sion and reception cannot be resumed if bit
OER is set to 1.
See figure 10-18 for details on overrun error
processing.
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