Timer C Operation States - Hitachi H8/3937 Series Hardware Manual

9.3.4

Timer C Operation States

Table 9-7 summarizes the timer C operation states.
Table 9-7 Timer C Operation States
Operation Mode Reset
TCC Interval Reset
Auto reload Reset
TMC Reset
Note: When øw/4 is selected as the TCC internal clock in active mode or sleep mode, since
*
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø (s). When the counter is operated in subactive mode or subsleep mode, either
select øw/4 as the internal clock or select an external clock. The counter will not
operate on any other internal clock. If øw/4 is selected as the internal clock for the
counter when øw/8 has been selected as subclock ø
operate on the same cycle, and the operation of the least significant bit is unrelated to
the operation of the counter.
Active Sleep Watch
Functions Functions Halted
Functions Functions Halted
Functions Retained Retained
Sub- Sub-
active sleep Standby
Functions/ Functions/ Halted
Halted* Halted*
Functions/ Functions/ Halted
Halted* Halted*
Functions Retained Retained
, the lower 2 bits of the counter
SUB
Module
Standby
Halted
Halted
Retained
195