Hitachi H8/3937 Series Hardware Manual page 358

See 12.5.4, Operation of a Temporary Address for details. The FLEX decoder will increment the
all frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received.
When the host determines that a message associated with a temporary address, or a fragmented
message has ended, then the appropriate temporary address counter or all frame mode counter
should be decremented by writing an All Frame Mode Packet to the FLEX decoder in order to exit
the all frame mode, thereby improving battery life. See 12.5.3, Building a Fragmented Message
for details. Neither the temporary address enable counters nor the all frame mode counter can be
incremented past the value 127 (i.e. it will not roll-over) or decremented past the value 0. The
temporary address enable counters and the all frame mode counter are initialized to 0 at reset and
when the decoder is turned off. The ID of the All Frame Mode Packet is 3.
Table 12-6 All Frame Mode Packet Bit Assignments
Bit 7 Bit 6
Byte 3 0 0
Byte 2 DAF FAF
Byte 1 DTA DTA
15
Byte 0 DTA DTA
7
DAF: Decrement All Frame counter. Setting this bit decrements the all frame mode counter by
one. If a packet is sent with this bit clear, the all frame mode counter is not affected. (value after
reset =0)
FAF: Force All Frame mode. Setting this bit forces the FLEX decoder to enter all frame mode. If
this bit is clear, the FLEX decoder may or may not be in all frame mode depending on the status of
the all frame mode counter and the temporary address enable counters. This may be useful in
acquiring transmitted time information. (value after reset=0)
DTA: Decrement Temporary Address enable counter. When a bit in this word is set, the
corresponding temporary address enable counter is decremented by one. When a bit is cleared, the
corresponding temporary address enable counter is not affected. When a temporary address enable
counter reaches zero, the temporary address is disabled.(value after reset=0)
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Bit 5 Bit 4
0 0
0 0
DTA DTA
14 13
DTA DTA
6 5
Bit 3 Bit 2
0 0
0 0
DTA DTA
12 11
DTA DTA
4 3
Bit 1 Bit 0
1 1
0 0
DTA DTA
10 9
DTA DTA
2 1
8
0