Hitachi H8/3937 Series Hardware Manual page 78

Bits 4 to 0: IRQ to IRQ
4
Bits 4 to 0 enable or disable IRQ
Bit n
IENn Description
Disables interrupt requests from pin IRQn
0
Enables interrupt requests from pin IRQn
1
Note: IRQ
is an internal signal that performs interfacing to the FLEX™ decoder incorporated in
0
the chip.
3. Interrupt enable register 2 (IENR2)
Bit 7
IENDT
Initial value 0
Read/Write R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT Description
0 Disables direct transfer interrupt requests
1 Enables direct transfer interrupt requests
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD Description
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
66
interrupt enable (IEN4 to IEN0)
0
to IRQ interrupt requests.
4 0
6 5
IENAD —
0 0
R/W R/W
4 3
IENTG IENTFH IENTFL
0 0
R/W R/W R/W
(initial value)
(n = 4 to 0)
2 1 0
IENTC IENEC
0 0 0
R/W R/W
(initial value)
(initial value)