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5.4
Watch Mode
5.4.1
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, and the FLEX™ decoder. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules,
are retained. I/O ports keep the same states as before the transition.
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ
input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on the
settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0,
transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active
(medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to
active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is
supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch
mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
5.4.3
Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
5.4.4
Notes on External Input Signal Changes before/after Watch Mode
See 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
, or WKP
to WKP
) or by
0
7
0
109
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