Hitachi H8/3937 Series Hardware Manual page 79

Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG Description
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH Description
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL Description
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC Description
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Bit 0: Reserved bit
Bit 0 is reserved: it is always read as 0 and cannot be modified.
For details of SCI31 interrupt control, see 6. Serial control register 3 (SCR3) in section 10.3.2.
(initial value)
(initial value)
(initial value)
(initial value)
67