Hitachi H8/3937 Series Hardware Manual page 483

IENR1—Interrupt enable register 1
Bit 7
IENTA
Initial value 0
Read/Write R/W
Timer A interrupt enable
0 Disables timer A interrupt requests
1
6 5
IENS1 IENWP
0 0
R/W R/W
Wakeup interrupt enable
0 Disables WKP
1 Enables WKP
SCI1 interrupt enable
0 Disables SCI1 interrupt requests
1 Enables SCI1 interrupt requests
Note: SCI1 is an internal function that performs
interfacing to the FLEX™ decoder
incorporated in the chip.
Enables timer A interrupt requests
4 3
IEN4 IEN3
0 0
R/W R/W
IRQ to IRQ interrupt enable
4 0
0 Disables IRQ to IRQ
4
1 Enables IRQ to IRQ
4
Note: IRQ is an internal signal that performs
0
interfacing to the FLEX™ decoder incorporated
in the chip.
to WKP
7 0
to WKP
7 0
H'F3 System control
2 1
IEN2 IEN1 IEN0
0 0
R/W R/W R/W
interrupt requests
0
interrupt requests
0
interrupt requests
interrupt requests
0
0
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