Subsleep Mode; Transition To Subsleep Mode; Clearing Subsleep Mode - Hitachi H8/3937 Series Hardware Manual

5.5

Subsleep Mode

5.5.1

Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter and WDT is halted. As long as a minimum required voltage is applied, the contents of
CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are
retained. I/O ports keep the same states as before the transition.
5.5.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, SCI1, SCI32, SCI31,
IRQ to IRQ , WKP
4 0 7
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
To synchronize the interrupt request signal with the subclock, up to 2/ø
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
110
) or by a low input at the RES pin.
to WKP
0
(s) delay may occur
SUB