12.1.3 Functional Block Diagram - Hitachi H8/3937 Series Hardware Manual

12.1.3 Functional Block Diagram

S1-S7
7
S0/IFIN
EXTS0
EXTS1
SYMCLK
76.8 kHz
ø
DEC
or 160 kHz
Oscillator
CLKOUT
Clock
Generator
332
S1-S7
Receiver Control
S0
Demodulator &
IFIN
Data Slicer
Symbol Sync
Sync
Correlator
De-interleaver
Address
Comparator/
Correlator
Figure 12-3 Block Diagram
Internal
Control
Unit
Noise Detector
Error Corrector
Control/Status
Local Message
Filter
SPI Buffer
TESTD
External
RESET
Control
Unit
LOBAT
Registers
READY
SPI SPI
4