Table of Contents
Advertisement
Bits 4 to 0: IRQ
to IRQ
4
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated
signal edge is input
Note: IRQ
is an internal signal that performs interfacing to the FLEX™ decoder incorporated in
0
the chip.
5. Interrupt request register 2 (IRR2)
Bit
7
IRRDT
Initial value
0
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2
interrupt request flags (IRRI4 to IRRI0)
0
6
5
IRRAD
—
0
0
R/(W) *
R/W
4
3
IRRTG
IRRTFH
IRRTFL
0
0
R/(W) *
R/(W) *
R/(W) *
(initial value)
(n = 4 to 0)
2
1
0
IRRTC
IRREC
0
0
0
R/(W) *
R/(W) *
(initial value)
69
Advertisement
Table of Contents
