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TCSRW—Timer control/status register W
Bit
B6WI
Initial value
Read/Write
Watchdog timer on
0 Watchdog timer operation is disabled
1
Bit 2 write inhibit
0 Bit 2 is write-enabled
1
Bit 2 is write-protected
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1
Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1
Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1
Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
7
6
5
TCWE
B4WI
1
0
1
*
R
R/(W)
R
Watchdog timer reset
0 [Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1
Bit 0 is write-protected
Watchdog timer operation is enabled
H'B2
4
3
TCSRWE
B2WI
WDON
0
1
*
R/(W)
R
R/(W)
Watchdog timer
2
1
0
B0WI
WRST
0
1
0
*
R
R/(W)
*
445
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