Hitachi H8/3937 Series Hardware Manual page 214

Bit 3: Toggle output level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL Description
0 Low level
1 High level
Bits 2 to 0: Clock select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event
input.
Bit 2 Bit 1
CKSL2 CKSL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: 1. External event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
For details, see 1. IRQ edge select register (IEGR) in section 3.3.2.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register
1 (PMR1) is changed from 0 to 1 while the TMIF pin is low in order to change the TMIF
pin function.
202
Bit 0
CKSL0 Description
0 Counting on external event (TMIF) rising/falling
1
1 edge*
0
1 Not available
0 Internal clock: counting on ø/32
1 Internal clock: counting on ø/16
0 Internal clock: counting on ø/4
1 Internal clock: counting on øw/4
(initial value)
(initial value)
*: Don't care