Hitachi H8/3937 Series Hardware Manual page 314

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Sender
Receiver A
(ID = 01)
Serial
data
Figure 10-18 Example of Inter-Processor Communication Using Multiprocessor Format
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10-14 for details.
For details on the clock used in multiprocessor communication, see 10.3.3, 2. Operation in
Asynchronous Mode.
• Multiprocessor transmitting
Figure 10-19 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
302
Communication line
Receiver B
(ID = 02)
H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)
(Sending data H'AA to receiver A)
Receiver C
(ID = 03)
H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified buy the ID)
Receiver D
(ID = 04)
MPB: Multiprocessor bit

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