Hitachi H8/3937 Series Hardware Manual page 112

Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose ø
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1 Bit 0
MA1 MA0
0 0
0 1
1 0
1 1
2. System control register 2 (SYSCR2)
Bit 7
—
Initial value 1
Read/Write —
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (ø
generator is sampled, in relation to the oscillator clock (ø
generator. When ø
OSC
Bit 4
NESEL Description
0 Sampling rate is ø
1 Sampling rate is ø
100
/128, ø /64, ø
OSC OSC OSC
Description
ø /16
OSC
ø /32
OSC
ø /64
OSC
ø /128
OSC
6 5
— —
1 1
— —
= 6 to 10 MHz, clear NESEL to 0.
/16
OSC
/4
OSC
/32, or ø /16 as the operating clock in active
OSC
4 3
NESEL DTON
1 0
R/W R/W
W
) generated by the system clock pulse
OSC
(initial value)
2 1
MSON SA1
0 0
R/W R/W
) generated by the subclock pulse
(initial value)
0
SA0
0
R/W