Hitachi H8/3937 Series Hardware Manual page 331

Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
CKS Conversion Period
0 62/ø (initial value)
1 31/ø
Note: Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a
*
value of at least 12.4 µs.
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE Description
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note: The external trigger (ADTRG) edge is selected by bit INTEG4 of IEGR. See 1. IRQ
*
edge select register (IEGR) in 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Conversion Time
ø = 1 MHz
62 µs
31 µs
ø = 5 MHz
12.4 µs
—
(initial value)
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