Host-To-Decoder Packet Map - Hitachi H8/3937 Series Hardware Manual

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12.2.3

Host-to-Decoder Packet Map

The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID's
for all of the packets that can be sent to the FLEX decoder from the host.
Table 12-1 Host-to-Decoder Packet ID Map
Packet ID
(Hexadecimal)
00
01
02
03
04
05
06
07 - 0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C - 1F
20
21
22
23
24
336
Packet Type
Checksum
Configuration
Control
All Frame Mode
Operator Message Address Enables
Roaming Control Packet
Timing Control Packet
Reserved (Host should never send)
Receiver Line Control
Receiver Control Configuration (Off Setting)
Receiver Control Configuration (Warm Up 1 Setting)
Receiver Control Configuration (Warm Up 2 Setting)
Receiver Control Configuration (Warm Up 3 Setting)
Receiver Control Configuration (Warm Up 4 Setting)
Receiver Control Configuration (Warm Up 5 Setting)
Receiver Control Configuration (3200sps Sync Setting)
Receiver Control Configuration (1600sps Sync Setting)
Receiver Control Configuration (3200sps Data Setting)
Receiver Control Configuration (1600sps Data Setting)
Receiver Control Configuration (Shut Down 1 Setting)
Receiver Control Configuration (Shut Down 2 Setting)
Special (Ignored by FLEX decoder)
Frame Assignment (Frames 112 through 127)
Frame Assignment (Frames 96 through 111)
Frame Assignment (Frames 80 through 95)
Frame Assignment (Frames 64 through 79)
Frame Assignment (Frames 48 through 63)

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