Hitachi H8/3937 Series Hardware Manual page 461

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TCSRF—Timer control/status register F
Bit
7
OVFH
Initial value
0
R/(W) *
Read/Write
Timer overflow flag L
Counter clear H
0
1
Timer overflow interrupt enable H
TCFH overflow interrupt request is disabled
0
1
TCFH overflow interrupt request is enabled
Compare match flag H
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
6
5
CMFH
OVIEH
0
0
R/(W) *
R/W
Counter clear L
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
Compare match flag L
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
Setting conditions:
1
Set when the TCFL value matches the OCRFL value
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
1
Set when TCFL overflows from H'FF to H'00
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
H'B7
4
3
CCLRH
OVFL
CMFL
0
0
R/(W) *
R/(W) *
R/W
Timer F
2
1
0
OVIEL
CCLRL
0
0
0
R/W
R/W
449

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