Hitachi H8/3937 Series Hardware Manual page 282

Bit 2: Transmit end (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND Description
0 Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1 Transmission ended
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is
sent
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR Description
0 Data in which the multiprocessor bit is 0 has been received*
1 Data in which the multiprocessor bit is 1 has been received
Note: When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
*
affected and retains its previous state.
Bit 0: Multiprocessor bit transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT Description
0 A 0 multiprocessor bit is transmitted
1 A 1 multiprocessor bit is transmitted
270
(initial value)
(initial value)
(initial value)