Interface Timing And Ac Characteristics; Sdio/Gspi Timing; Sdio Default Mode Timing - Infineon Cypress CYW43353 Manual

18. Interface Ti ming and AC Characteristics

18.1 SDIO/gSPI Timing

18.1.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of
SDIO_CLK
Input
Output
Table 44. SDIO Bus Timing
Parameter
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
Clock high time
Clock rise time
Clock fall time
Input setup time
Input hold time
Output delay time – Data Transfer mode
Output delay time – Identification mode
Timing is based on CL  40pF load on CMD and Data.
1.
2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 32. SDIO Bus Timing (Default Mode)
1
Parameters (Default Mode)
SDIO CLK (All values are referred to minimum VIH and maximum VIL
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
Figure 32 and Table 44.
f
PP
t t
WL WH
t t
THL TLH
t t
ISU IH
t
ODLY
(max)
Symbol Minimum
fPP 0
fOD 0
tWL 10
tWH 10
tTLH –
tTHL –
tISU 5
tIH 5
tODLY 0
tODLY 0
t
ODLY
(min)
Typical Maximum
2
)
– 25
– 400
– –
– –
– 10
– 10
– –
– –
– 14
– 50
CYW43353
Unit
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
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