Infineon Cypress CYW43353 Manual page 12

Shaded areas are internal to the BCM 43353
WL_REG_ON
BT_REG_ON
VBAT
Average 275 mA
VDDIO
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 2. Typical Power Topology for CYW43353
Core Buck
Regulator
1.35V
CBUCK
Peak 600 mA
1.1V
LPLDO1
3 mA
Internal LNLDO 1.2V
80 mA
Internal LNLDO
1.2V
80 mA
1.2V
Internal VCOLDO
80 mA
Internal LNLDO 1.2V
80 mA
XTAL LDO
1.2V
30 mA
1.2V
LNLDO
100 mA
CLDO
Peak 300 mA
1.2V– 1.1V
Average 175 mA
(Bypass in deep
sleep)
MEMLPLDO
VDDIO
3 mA
BTLDO2P5
2.5V
Peak 70 mA
Average 15 mA
LDO3P3
3.3V
Peak 800–450 mA
Internal LNLDO
Average 200 mA
25 mA
Internal LNLDO
8 mA
CYW43353
WL RF – AFE
WL RF – TX (2.4 GHz, 5 GHz)
WL RF – LOGEN (2.4 GHz, 5 GHz)
WL RF – RX/LNA (2.4 GHz, 5 GHz)
WL RF – XTAL
WL RF – RFPLL PFD/MMD
BT RF
DFE/DFLL
PLL/RXTX
WLAN BBPLL/DFLL
WLAN/BT/CLB/Top, always on
WL OTP
WL PHY
WL DIGITAL
BT DIGITAL
WL/BT SRAMs
0.9V
BT CLASS 1 PA
WL PA/PAD (2.4 GHz, 5 GHz)
VDDIO_RF
WL OTP 3.3V
WL RF – VCO
WL RF – CP
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