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9.2.2 gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up
WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43353 is ready for data trans-
fer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be fol-
lowed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any
information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the
cause of interrupt and then take necessary actions.
9.2.3 Boot-Up Sequence
After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to poll with a read com-
mand to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct
register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit
(F0 reg 0x00 bit 7). The wakeup-WLAN issues a clock request to the PMU.
For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once that is available,
the host must write to a PMU register to set the crystal frequency, which turns on the PLL. After the PLL is locked, the chipActive
interrupt is issued to the host. This interrupt indicates the device awake/ready status. See
In
Table
14, the following notation is used for register access:
R: Readable from host and CPU
■
W: Writable from host
■
U: Writable from CPU
■
Table 14. gSPI Registers
Address
Register
x0000
Word length
Endianness
High-speed mode
Interrupt polarity
Wake-up
x0001
Response delay
x0002
Status enable
Interrupt with status
Response delay for all
x0003
Reserved
Document Number: 002-14949 Rev. *G
PRELIMINARY
Bit
Access
Default
0
R/W/U
0
1
R/W/U
0
4
R/W/U
1
5
R/W/U
1
7
R/W
0
7:0
R/W/U
8'h04
0
R/W
1
1
R/W
0
2
R/W
0
–
–
–
Table 14
Description
0: 16 bit word length
1: 32 bit word length
0: Little Endian
1: Big Endian
0: Normal mode. RX and TX at different edges.
1: High speed mode. RX and TX on same edge (default).
0: Interrupt active polarity is low
1: Interrupt active polarity is high (default)
A write of 1 will denote a wake-up command from the host to the
device. This will be followed by an F2 Interrupt from the gSPI
device to the host, indicating device awake status.
Configurable read response delay in multiples of 8 bits
0: no status sent to host after read/write
1: status sent to host after read/write
0: do not interrupt if status is sent
1: interrupt host even if status is sent
0: response delay applicable to F1 read only
1: response delay applicable to all function read
–
CYW43353
for information on gSPI registers.
Page 47 of 113
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