Infineon Cypress CYW43353 Manual page 65

Table 20. Multiplexed GPIO Signals
Pin Name
UART_CTS_N I
UART_RTS_N O
UART_RXD I
UART_TXD O
PCM_IN I
PCM_OUT O
PCM_SYNC I/O
PCM_CLK I/O
GPIO[7:0] I/O
A_GPIO[7:0] I/O
I2S_MSDO O
I2S_MWS O
I2S_MSCK O
I2S_SSCK I
I2S_SSDO O
I2S_SWS I
I2S_SSDI/MSDI I
STATUS O
TX_CON_FX I
RF_ACTIVE O
LINK_IND O
CLK_REQ O
SF_SPI_CLK O
SF_MISO I
SF_MOSI O
SF_SPI_CSN O
Document Number: 002-14949 Rev. *G
PRELIMINARY
Type
Host UART clear to send.
Device UART request to send.
Device UART receive data.
Host UART transmit data.
PCM data input.
PCM data output.
PCM sync signal, can be master (output) or slave (input).
PCM clock, can be master (output) or slave (input).
General-purpose I/O.
A group general-purpose I/O.
2
I S master data output.
2
I S master word select.
2
I S master clock.
2
I S slave clock.
2
I S slave data output.
2
I S slave word select.
2
I S slave/master data input.
Signals Bluetooth priority status.
WLAN-BT coexist. Transmission confirmation; permission for BT to transmit.
WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots.
BT receiver/transmitter link indicator.
WLAN/BT clock request output.
SFlash SCLK: serial clock (output from master).
SFlash MISO; SOMI: master input, slave output (output from slave).
SFlash MOSI; SIMO: master output, slave input (output from master).
SFlash SS: slave select (active low, output from master).
Description
CYW43353
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