Infineon Cypress CYW43353 Manual page 47

Figure 24. gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian)
Write
Write‐Read
Read
Table 13. gSPI Status Field Details
Bit
0 Data not available
1 Underflow
2 Overflow
3 F2 interrupt
4 F3 interrupt
5 F2 RX Ready
6 F3 RX Ready
7 Reserved
8 F2 Packet Available
9:19 F2 Packet Length
20 F3 Packet Available
21:31 F3 Packet Length
Document Number: 002-14949 Rev. *G
PRELIMINARY
cs
sclk
mosi
C31 C31 C31 C1 C1 C1
miso
Command 32 bits
cs
sclk
mosi C31 C31 C31
C0 C0 C0
miso
Command 32 bits
cs
sclk
mosi
C31 C31 C31 C0 C0 C0
miso
Command 32 bits
Name
C0 C0 C0 D31 D31 D31 D1 D1 D1 D0 D0 D0
Write Data 16*n bits
D31 D31 D31 D1 D1 D1
Read Data 16*n bits
D31 D31 D31 D1 D1 D1
Read Data 16*n bits
The requested read data is not available
FIFO underflow occurred due to current (F2, F3) read command
FIFO overflow occurred due to current (F1, F2, F3) write command
F2 channel interrupt
F3 channel interrupt
F2 FIFO is ready to receive data (FIFO empty)
F3 FIFO is ready to receive data (FIFO empty)
–
Packet is available/ready in F2 TX FIFO
Length of packet available in F2 FIFO
Packet is available/ready in F3 TX FIFO
Length of packet available in F3 FIFO
S31 S31 S31 S1 S1 S1 S0 S0 S0
Status 32 bits
S31 S31 S31 S0 S0 S0
D0 D0 D0
Status 32 bits
D0 D0 D0 S31 S31 S31 S0 S0 S0
Status 32 bits
Description
CYW43353
Page 46 of 113