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9. WLAN Host Interfaces
9.1 SDIO v3.0
The CYW43353 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■
HS: High speed up to 50 MHz (3.3V signaling).
■
SDR12: SDR up to 25 MHz (1.8V signaling).
■
SDR25: SDR up to 50 MHz (1.8V signaling).
■
SDR50: SDR up to 100 MHz (1.8V signaling).
■
SDR104: SDR up to 208 MHz (1.8V signaling).
■
DDR50: DDR up to 50 MHz (1.8V signaling).
■
Note: The CYW43353 is backward compatible with SDIO v2.0 host interfaces.
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different
from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided.
SDIO mode is enabled by strapping options. Refer to
The following three functions are supported:
Function 0 Standard SDIO function (Max. BlockSize/ByteCount = 32B)
■
Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
■
(Max. BlockSize/ByteCount = 64B)
Function 2 WLAN Function for efficient WLAN packet transfer through DMA
■
(Max. BlockSize/ByteCount = 512B)
9.1.1 SDIO Pins
Table 12. SDIO Pin Description
SD 4-Bit Mode
DATA0
Data line 0
DATA1
Data line 1 or Interrupt
DATA2
Data line 2 or Read Wait
DATA3
Data line 3
CLK
Clock
CMD
Command line
Document Number: 002-14949 Rev. *G
PRELIMINARY
Table 16
SD 1-Bit Mode
DATA
Data line
IRQ
Interrupt
RW
Read Wait
N/C
Not used
CLK
Clock
CMD
Command line
Figure 17. Signal Connections to SDIO Host (SD 4-Bit Mode)
SD Host
WLAN GPIO Functions and Strapping Options.
DO
IRQ
NC
CS
SCLK
DI
CLK
CMD
CYW43353
DAT[3:0]
CYW43353
gSPI Mode
Data output
Interrupt
Not used
Card select
Clock
Data input
Page 41 of 113
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