Infineon Cypress CYW43353 Manual page 100

18.1.3.3. Device Output Timing
SDIO_CLK
CMD output
DAT[3:0] output
Table 48. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)
Symbol
t –
ODLY
t –
ODLY
t 1.5
OH
SDIO_CLK
CMD output
DAT[3:0] output
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 36. SDIO Bus Output Timing (SDR Modes up to 100 MHz)
t
Minimum Maximum
7.5
14.0
–
Figure 37. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)
t
CLK
ODLY
Unit
ns t ≥ 10 ns C
CLK
ns t ≥ 20 ns C
CLK
ns Hold time at the t
t
CLK
t t
OP ODW
t
OH
Comments
= 30 pF using driver type B for SDR50
L
= 40 pF using for SDR12, SDR25
L
(min) C = 15 pF
ODLY L
CYW43353
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