Infineon Cypress CYW43353 Manual page 33

7.1.6.3. Long Frame Sync, Master Mode
PCM_BCLK
PCM_SYNC
PCM_OUT
5
PCM_IN
Table 7. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No.
1 PCM bit clock frequency
2 PCM bit clock LOW
3 PCM bit clock HIGH
4 PCM_SYNC delay
5 PCM_OUT delay
6 PCM_IN setup
7 PCM_IN hold
8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT
becoming high impedance
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 11. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
4
Bit 0 Bit 1
Bit 0
Bit 1
Characteristics
2
3
8
HIGH IMPEDANCE
7
6
Minimum Typical Maximum
– – 12
41 – –
41 – –
0 – 25
0 – 25
8 – –
8 – –
0 – 25
CYW43353
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
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