1. Manuals
  2. Brands
  3. Infineon Manuals
  4. Single board computers
  5. Cypress CYW43353
  6. Manual

Infineon Cypress CYW43353 Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as "Cypress" document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com

Advertisement

Table of Contents
loading

Related Manuals for Infineon Cypress CYW43353

Summary of Contents for Infineon Cypress CYW43353

  • Page 1 The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 PRELIMINARY CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications General Description ® The Cypress CYW43353 single-chip device provides the highest level of integration for Automotive and Industrial connectivity systems with integrated single-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth 4.1. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 433.3 Mbps.
  • Page 3 PRELIMINARY CYW43353 Features IEEE 802.11x Key Features IEEE 802.11ac compliant. ™ ■ Integrated ARMCR4 processor with tightly coupled mem- ■ ory for complete WLAN subsystem functionality, minimizing Single-stream spatial multiplexing up to 433.3 Mbps data ■ the need to wake up the applications processor for standard rate.
  • Page 4 PRELIMINARY CYW43353 General Features ™ ™ and WPA2 (Personal) support for powerful ❐ encryption and authentication Supports battery voltage range from 3.0V to 4.8 supplies with ■ AES and TKIP in hardware for faster data encryption and internal switching regulator. ❐...

  • Page 5: Table Of Contents

    PRELIMINARY CYW43353 Contents 1. Overview ............6 5.8 Fast Connection (Interlaced Page and Inquiry Scans) ..............26 1.1 Overview ............. 6 6. Microprocessor and Memory Unit for 1.2 Features .............. 8 Bluetooth ............27 1.3 Standards Compliance ........8 6.1 RAM, ROM, and Patch Memory ......27 1.4 Automotive and Industrial Usage Model .....
  • Page 6 PRELIMINARY CYW43353 12. Pinout and Signal Descriptions..... 56 17. System Power Consumption ......92 12.1 Ball Maps ............56 17.1 WLAN Current Consumption ......92 12.2 Signal Descriptions ........... 57 17.2 Bluetooth Current Consumption ......94 12.3 WLAN GPIO Signals and Strapping Options ..62 18.

  • Page 7: Overview

    1. Overview 1.1 Overview The Cypress CYW43353 single-chip device provides the highest level of integration for automotive and industrial wireless connectivity systems, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, and Bluetooth 4.1 + enhanced data rate (EDR). It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for platform flexibility in size, form, and function.
  • Page 8 PRELIMINARY CYW43353 Figure 1. CYW43353 Block Diagram SECI UART and GCI-GPIOs WL_HOST_WAKE WL_DEV_WAKE JTAG Other GPIOs WLAN RAM RAM768KB Sharing SDIOD ROM640KB SDIO 3.0 BT_HOST_WAKE UART BT_DEV_WAKE UART ARMCM3 ARMCR4 Other GPIOs BT Access WLAN WLAN AXI2AHB Master AHB2AXI Registers Slave Chip WL_REG_ON...

  • Page 9: Features

    PRELIMINARY CYW43353 1.2 Features The CYW43353 supports the following features: IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation ■ Bluetooth v4.1 + EDR with integrated Class 1 PA ■ Concurrent Bluetooth and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■...

  • Page 10: Automotive And Industrial Usage Model

    PRELIMINARY CYW43353 Security: ■ ❐ ™ Personal ❐ ™ WPA2 Personal ❐ ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ AES (Hardware Accelerator) ❐ TKIP (HW Accelerator) ❐ CKIP (SW Support) ❐ Proprietary Protocols: ■ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ❐...

  • Page 11: Power Supplies And Power Management

    PRELIMINARY CYW43353 2. Power Supplies and Power Management 2.1 Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43353. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
  • Page 12 PRELIMINARY CYW43353 Figure 2. Typical Power Topology for CYW43353 Internal LNLDO 1.2V WL RF – AFE Shaded areas are internal to the BCM 43353 80 mA Internal LNLDO 1.2V WL RF – TX (2.4 GHz, 5 GHz) 80 mA 1.2V Internal VCOLDO WL RF – LOGEN (2.4 GHz, 5 GHz) 80 mA Internal LNLDO 1.2V WL RF – RX/LNA (2.4 GHz, 5 GHz) 80 mA XTAL LDO 1.2V WL RF – XTAL 30 mA WL RF –...

  • Page 13: Wlan Power Management

    PRELIMINARY CYW43353 2.3 WLAN Power Management All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43353 integrated RAM is a high Vt memory with dynamic clock control.

  • Page 14: Power-Off Shutdown

    PRELIMINARY CYW43353 During each clock cycle, the PMU sequencer performs the following actions: Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource ■...

  • Page 15: Frequency References

    PRELIMINARY CYW43353 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external fre- quency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43353 can use an external crystal to provide a frequency reference.

  • Page 16: External Frequency Reference

    PRELIMINARY CYW43353 3.2 External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used. The recommended default frequency is 37.4 MHz. This must meet the phase noise requirements listed in Table If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown Figure 4.

  • Page 17: Frequency Selection

    PRELIMINARY CYW43353 Table 2. Crystal Oscillator and External Clock—Requirements and Performance (Cont.) External Frequency Crystal Reference Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Units 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz Phase noise 37.4 MHz clock at 100 kHz offset –...

  • Page 18: External 32.768 Khz Low-Power Oscillator

    PRELIMINARY CYW43353 3.4 External 32.768 kHz Low-Power Oscillator The CYW43353 uses a secondary low-frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is required. Use a precision external 32.768 kHz clock that meets the requirements listed in Table Table 3.

  • Page 19: Bluetooth Subsystem Overview

    4. Bluetooth Su bsystem Overview The Cypress CYW43353 is a Bluetooth 4.1 + EDR-compliant, baseband processor/2.4 GHz transceiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth solution.

  • Page 20: Bluetooth Radio

    PRELIMINARY CYW43353 Bluetooth clock request ❐ Bluetooth standard sniff ❐ Deep-sleep modes and software regulator shutdown ❐ TCXO input and autodetection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used ■ during power save mode for better timing accuracy. 4.2 Bluetooth Radio The CYW43353 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems.

  • Page 21: Receiver Signal Strength Indicator

    PRELIMINARY CYW43353 4.2.7 Receiver Signal Strength Indicator The radio portion of the CYW43353 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the control- ler can determine whether the transmitter should increase or decrease its output power. 4.2.8 Local Oscillator Generation Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.

  • Page 22: Bluetooth Baseband Core

    PRELIMINARY CYW43353 5. Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and pack- ages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets.

  • Page 23: Link Control Layer

    PRELIMINARY CYW43353 5.3 Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are acti- vated or configured by the command controller to perform the link control tasks.

  • Page 24: Bluetooth Power Management Unit

    PRELIMINARY CYW43353 5.5 Bluetooth Power Management Unit The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the CYW43353 are: RF Power Management ■...

  • Page 25: Bbc Power Management

    PRELIMINARY CYW43353 Figure 5. Startup Signaling Sequence Host IOs VDDIO unconfigured Host IOs configured HostResetX BT_GPIO_0 (BT_DEV_WAKE) BT_REG_ON BTH IOs BTH IOs configured unconfigured BT_GPIO_1 (BT_HOST_WAKE) Host drives this low. BT_UART_CTS_N BTH device drives this low indicating BT_UART_RTS_N transport is ready. CLK_REQ_OUT Driven Pulled...

  • Page 26: Wideband Speech

    PRELIMINARY CYW43353 During the low-power shut-down state, provided VDDIO remains applied to the CYW43353, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the CYW43353 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes.

  • Page 27: Audio Rate-Matching Algorithms

    PRELIMINARY CYW43353 Figure 7. CVSD Decoder Output Waveform After Applying PLC 5.5.6 Audio Rate-Matching Algorithms The CYW43353 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio stream jitter that may be present when the rate of audio data coming from the host is not the same as the Bluetooth audio data rates. 5.5.7 Codec Encoding The CYW43353 can support SBC and mSBC encoding and decoding for wideband speech.

  • Page 28: Microprocessor And Memory Unit For Bluetooth

    PRELIMINARY CYW43353 6. Microprocessor and Memory Unit for Bluetooth ® ™ The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller interface (HCI). The ARM core is paired with a memory unit that contains 608 KB of ROM memory for program storage and boot ROM, 192 KB of RAM for data scratch-pad and patch RAM code.

  • Page 29: Bluetooth Peripheral Transport Unit

    PRELIMINARY CYW43353 7. Bluetooth Peripher a l Tr a n s p o r t U n i t 7.1 PCM Interface The CYW43353 supports two independent PCM interfaces that share pins with the I S interfaces. The PCM Interface on the CYW43353 can connect to linear PCM codec devices in master or slave mode.
  • Page 30 PRELIMINARY CYW43353 Figure 8. Functional Multiplex Data Diagram 1 frame BT SCO 1 Rx BT SCO 2 Rx BT SCO 3 Rx FM right FM left PCM_OUT BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx PCM_IN FM right FM left PCM_SYNC...

  • Page 31: Pcm Interface Timing

    PRELIMINARY CYW43353 7.1.6 PCM Interface Timing 7.1.6.1. Short Frame Sync, Master Mode Figure 9. PCM Timing Diagram (Short Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 5. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. Characteristics Minimum Typical...
  • Page 32 PRELIMINARY CYW43353 7.1.6.2. Short Frame Sync, Slave Mode Figure 10. PCM Timing Diagram (Short Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 6. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 33 PRELIMINARY CYW43353 7.1.6.3. Long Frame Sync, Master Mode Figure 11. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE Bit 0 Bit 1 Bit 0 Bit 1 PCM_IN Table 7. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No. Characteristics Minimum Typical...
  • Page 34 PRELIMINARY CYW43353 7.1.6.4. Long Frame Sync, Slave Mode Figure 12. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 Bit 0 Bit 1 PCM_IN Table 8. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical...

  • Page 35: Uart Interface

    PRELIMINARY CYW43353 7.2 UART Interface The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The inter- face features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.
  • Page 36 PRELIMINARY CYW43353 Figure 13. UART Timing UART_CTS_N UART_TXD Midpoint of STOP bit Midpoint of STOP bit UART_RXD UART_RTS_N Table 10. UART Timing Specifications Ref No. Characteristics Min. Typ. Max. Unit Delay time, UART_CTS_N low to UART_TXD valid – – Bit period Setup time, UART_CTS_N high before midpoint of stop bit –...

  • Page 37: S Interface

    PRELIMINARY CYW43353 7.3 I S Interface The CYW43353 supports two independent I S digital audio ports. The I S signals are: S clock: I S SCK ❐ S Word Select: I S WS ❐ S Data Out: I S SDO ❐...
  • Page 38 PRELIMINARY CYW43353 The system clock period T must be greater than T and T because both the transmitter and receiver have to be able to handle the data transfer rate. 2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t and t are specified with respect to T.
  • Page 39 PRELIMINARY CYW43353 Figure 15. I S Receiver Timing > 0.35T > 0.35 = 2.0V = 0.8V > 0.2T > 0 SD and WS T = Clock period = Minimum allowed clock period for transmitter T > T Document Number: 002-14949 Rev. *G Page 38 of 113...

  • Page 40: Wlan Global Functions

    PRELIMINARY CYW43353 8. WLAN Global Functions 8.1 WLAN CPU and Memory Subsystem ™ The CYW43353 WLAN section includes an integrated ARM Cortex-R4 32-bit processor with internal RAM and ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response features.

  • Page 41: External Coexistence Interface

    PRELIMINARY CYW43353 8.4 External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance. Figure 16 shows the LTE coexistence interface.

  • Page 42: Wlan Host Interfaces

    PRELIMINARY CYW43353 9. WLAN Host Interfaces 9.1 SDIO v3.0 The CYW43353 WLAN section supports SDIO version 3.0, including the new UHS-I modes: DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). ■ HS: High speed up to 50 MHz (3.3V signaling). ■...

  • Page 43: Generic Spi Mode

    PRELIMINARY CYW43353 Figure 18. Signal Connections to SDIO Host (SD 1-Bit Mode) DATA SD Host CYW43353 Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line.

  • Page 44: Spi Protocol

    PRELIMINARY CYW43353 9.2.1 SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes. Figure 20 Figure 21 show the basic write and write/read commands. Figure 20. gSPI Write Protocol Figure 21. gSPI Read Protocol Document Number: 002-14949 Rev.
  • Page 45 PRELIMINARY CYW43353 9.2.1.1. Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure Figure 22. gSPI Command Structure BCM_SPID Command Structure Ad dres s – 17 bits Ad dres s – 17 bits P acket length - 11b its * P acket length - 11b its * * 11’...
  • Page 46 PRELIMINARY CYW43353 9.2.1.5. Status The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in reducing the number of interrupts to the host.
  • Page 47 PRELIMINARY CYW43353 Figure 24. gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) Write sclk mosi miso Command 32 bits Write Data 16*n bits Status 32 bits Write‐Read sclk mosi miso Read Data 16*n bits Status 32 bits Command 32 bits Read sclk mosi miso Command 32 bits Read Data 16*n bits Status 32 bits Table 13. gSPI Status Field Details Name Description Data not available...

  • Page 48: Gspi Host-Device Handshake

    PRELIMINARY CYW43353 9.2.2 gSPI Host-Device Handshake To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43353 is ready for data trans- fer.
  • Page 49 PRELIMINARY CYW43353 Table 14. gSPI Registers (Cont.) Address Register Access Default Description x0004 Interrupt register Requested data not available; Cleared by writing a 1 to this location F2/F3 FIFO underflow due to last read F2/F3 FIFO overflow due to last write F2 packet available F3 packet available F1 overflow due to last write...
  • Page 50 PRELIMINARY CYW43353 Figure 25. WLAN Boot-Up Sequence VBAT* VDDIO WL_REG_ON < 950 µs VDDC (from internal PMU) < 104 ms  Internal POR After a fixed delay following Internal POR and WL_REG_ON going high,  < 4 ms  the device responds to host F0 (address 0x14) reads. Device requests for reference clock 8 ms  After 8 ms the reference clock is  assumed to be up.  Access to PLL  registers is possible. Host Interaction: Host polls F0 (address 0x14) until it reads a  predefined pattern. Host sets wake‐up‐wlan bit and  waits 8 ms, the maximum time for  reference clock availability. After 8 ms, host programs PLL  registers to set crystal frequency Chip active interrupt is asserted after the PLL locks Host downloads  code. *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Document Number: 002-14949 Rev. *G Page 49 of 113...

  • Page 51: Wireless Lan Mac And Phy

    PRELIMINARY CYW43353 10. Wireless LAN MAC and PHY 10.1 IEEE 802.11ac MAC The CYW43353 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without com- promising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing syn- chronization.

  • Page 52: Psm

    PRELIMINARY CYW43353 Statistics counters for MIB support ■ 10.1.1 PSM The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are pre- dominant in implementations of communication protocols.

  • Page 53: Ifs

    PRELIMINARY CYW43353 10.1.5 IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These tim- ers provide precise timing to the TXE to begin frame transmission.
  • Page 54 PRELIMINARY CYW43353 The key PHY features include: Programmable data rates from MCS0–9 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in IEEE 802.11ac ■ Supports Optional Short GI mode in TX and RX ■ TX and RX LDPC for improved range and power efficiency ■...

  • Page 55: Wlan Radio Subsystem

    PRELIMINARY CYW43353 11. W LAN Radio Subsystem The CYW43353 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands.
  • Page 56 PRELIMINARY CYW43353 Figure 28. Radio Functional Block Diagram W L D AC W L P A W L P AD W L PG A W L TX LP F W L TX G ‐M ixer W L D A C W L A ‐P A W L A ‐PA D W L A‐P G A W L TX LPF W L TX  A ‐M ixer...

  • Page 57: Pinout And Signal Descriptions

    PRELIMINARY CYW43353 12. Pinout and Signal Descriptions 12.1 Ball Maps Figure 29 shows the WLBGA ball map. Figure 29. 145-Ball WLBGA (Top View) NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT SR_PVSS SR_VLX WL_REG_ON LPO_IN...

  • Page 58: Signal Descriptions

    PRELIMINARY CYW43353 12.2 Signal Descriptions The signal name, type, and description of each pin in the CYW43353 is listed in Table 15. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
  • Page 59 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description WLAN GPIO Interface Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific functions. See Table 21, “CYW43353 GPIO/SDIO Alternative Signal Functions,”...
  • Page 60 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description Bluetooth GPIO BT_AGPIO BT analog GPIO pin. Miscellaneous WL_REG_ON Used by PMU to power up or power down the internal CYW43353 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset.
  • Page 61 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description WLAN Supplies WRF_WL_LNLDOIN_VDD1P5 LNLDO 1.35V supply. WRF_SYNTH_VBAT_VDD3P3 Synth VDD 3.3V supply. WRF_PADRV_VBAT_VDD3P3 PA Driver VBAT supply. WRF_PA5G_VBAT_VDD3P3 5 GHz PA 3.3V VBAT supply. WRF_PA2G_VBAT_VDD3P3 2 GHz PA 3.3V VBAT supply. WRF_MMD_VDD1P2 1.2V supply.
  • Page 62 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description PMU_AVSS Quiet ground. AGND12PLL/HSIC_AGNDPLL PLL ground. BT_PAVSS Bluetooth PA ground. BT_IFVSS Bluetooth IF block ground. BT_PLLVSS Bluetooth PLL ground. BT_VCOVSS Bluetooth VCO ground. VSSF Ground. VSSF Ground.

  • Page 63: Wlan Gpio Signals And Strapping Options

    PRELIMINARY CYW43353 12.3 WLAN GPIO Signals and Strapping Options The pins listed in Table 16 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.

  • Page 64: Multiplexed Bluetooth Gpio Signals

    PRELIMINARY CYW43353 12.3.1 Multiplexed Bluetooth GPIO Signals The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used as GPIOs or for other Bluetooth interface signals such as S. The specific function for a given BT_GPIO_X pin is chosen by programming the Pad Function Control register for that specific pin. Table 19 shows the possible options for each BT_GPIO_X pin.
  • Page 65 PRELIMINARY CYW43353 Table 20. Multiplexed GPIO Signals Pin Name Type Description UART_CTS_N Host UART clear to send. UART_RTS_N Device UART request to send. UART_RXD Device UART receive data. UART_TXD Host UART transmit data. PCM_IN PCM data input. PCM_OUT PCM data output. PCM_SYNC PCM sync signal, can be master (output) or slave (input).

  • Page 66: Gpio/Sdio Alternative Signal Functions

    PRELIMINARY CYW43353 12.4 GPIO/SDIO Alternative Signal Functions Table 21. CYW43353 GPIO/SDIO Alternative Signal Functions Pins WLBGA SDIO GPIO_0 WL_HOST_WAKE GPIO_1 WL_DEV_WAKE GPIO_2 TCK, GCI_GPIO_1, or UART RX GPIO_3 TMS or GCI_GPIO_0 GPIO_4 TDI or SECI_IN GPIO_5 TDO or SECI_OUT GPIO_6 TRST_L or UART TX GPIO_7 [Strap, tied High]...

  • Page 67: I/O States

    PRELIMINARY CYW43353 12.5 I/O States The following notations are used in Table I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■ NoPull = Neither pulled up nor pulled down ■...
  • Page 68 PRELIMINARY CYW43353 Table 22. I/O States (Cont.) Power-down Out-of-Reset; (WL_REG_ON High (BT_REG_ON and Before SW Download and BT_REG_ON = Keeper Low Power State/Sleep WL_REG_ON Held (BT_REG_ON High; 0) and VDDIOs Are Name Active Mode (All Power Present) Low) WL_REG_ON High) Present Power Rail BT_PCM_IN...
  • Page 69 PRELIMINARY CYW43353 Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in Power-down state. If there is no keeper, and it is an input and there is Nopull, then the pad should be driven to prevent leakage due to floating pad (SDIO_CLK, for example). In the Power-down state (xx_REG_ON=0): High-Z;...

  • Page 70: Dc Characteristics

    PRELIMINARY CYW43353 13. DC Ch aracteristics 13.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 23 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

  • Page 71: Electrostatic Discharge Specifications

    PRELIMINARY CYW43353 13.3 Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 25.
  • Page 72 PRELIMINARY CYW43353 Table 26. Recommended Operating Conditions and DC Characteristics (Cont.) Value Typic Parameter Symbol Minimum Maximum Unit Output low voltage @ 2 mA – – 0.45 For VDDIO = 3.3V: Input high voltage 2.00 – – Input low voltage –...

  • Page 73: Bluetooth Rf Specifications

    PRELIMINARY CYW43353 1 4 . B l u e t o o t h R F Specifications Unless otherwise stated, limit values apply for the conditions specified in Table 24, “Environmental Ratings,” Table 26, “Recom- mended Operating Conditions and DC Characteristics,”.
  • Page 74 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit C/I image channel GFSK, 0.1% BER – –31 – C/I 1-MHz adjacent to image channel GFSK, 0.1% BER – –46 – /4–DQPSK, 0.1% BER C/I co-channel –...
  • Page 75 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 824–849 MHz WCDMA – –11.4 – 880–915 MHz E-GSM – –10.4 – 880–915 MHz WCDMA – –10.2 – 1710–1785 MHz GSM1800 – –15.8 – 1710–1785 MHz WCDMA –...
  • Page 76 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Spurious Emissions 30 MHz–1 GHz – –95 –62 1–12.75 GHz – –70 –47 851–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz –...
  • Page 77 PRELIMINARY CYW43353 Table 28. Bluetooth Transmitter RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Noise Floor 65–108 MHz FM RX – –147 – dBm/Hz 776–794 MHz CDMA2000 – –147 – dBm/Hz 869–960 MHz cdmaOne, GSM850 – –147 – dBm/Hz 925–960 MHz E-GSM...
  • Page 78 PRELIMINARY CYW43353 Table 29. Local Oscillator Performance Parameter Minimum Typical Maximum Unit LO Performance s Lock time – – Initial carrier frequency tolerance – ±25 ±75 Frequency Drift DH1 packet – ±8 ±25 DH3 packet – ±8 ±40 DH5 packet –...

  • Page 79: Wlan Rf Specifications

    PRELIMINARY CYW43353 15. WLAN RF Sp ecifications 15.1 Introduction The CYW43353 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This sec- tion describes the RF characteristics of the 2.4 GHz and 5 GHz radio. Unless otherwise stated, limit values apply for the conditions specified inTable 24, “Environmental Ratings,”...

  • Page 80: Wlan 2.4 Ghz Receiver Performance Specifications

    PRELIMINARY CYW43353 15.3 WLAN 2.4 GHz Receiver Performance Specifications Note: The specifications in Table 32 are specified at the RF port and include the use of an external FEM with LNA from Cypress’s approved-vendor list (AVL), unless otherwise specified. Results with FEMs that are not on Cypress’s AVL are not guaranteed. Table 32.
  • Page 81 PRELIMINARY CYW43353 Table 32. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11ac 40 MHz channel spacing for all MCS rates MCS0 – –91.5 – a,5. (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns MCS1 –...
  • Page 82 PRELIMINARY CYW43353 Table 32. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection—DSSS Desired and interfering signal 30 MHz apart (Difference between interfering and 1 Mbps DSSS –74 dBm – – desired signal at 8% PER for 1024 2 Mbps DSSS –74 dBm –...

  • Page 83: Wlan 2.4 Ghz Transmitter Performance Specifications

    PRELIMINARY CYW43353 15.4 WLAN 2.4 GHz Transmitter Performance Specifications Note: The specifications in Table 33 include the use of the CYW43353's internal PAs and are specified at the chip port. Table 33. WLAN 2.4 GHz Transmitter Performance Specifications Minimu Maximu Parameter Condition/Notes Typical...

  • Page 84: Wlan 5 Ghz Receiver Performance Specifications

    PRELIMINARY CYW43353 15.5 WLAN 5 GHz Receiver Performance Specifications Note: The specifications in Table 34 are specified at the RF port and include the use of an external FEM with LNA from Cypress’s approved-vendor list (AVL), unless otherwise specified. Results with FEMs that are not on Cypress’s AVL are not guaranteed. Table 34.
  • Page 85 PRELIMINARY CYW43353 Table 34. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11ac 40 MHz channel spacing for all MCS rates (10% PER for 4096 octet PSDU) MCS0 – –90.5 – Defined for default parameters: 800 ns MCS1 –...
  • Page 86 PRELIMINARY CYW43353 Table 34. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Maximum receive level @ 6, 9, 12 Mbps –9.5 – – @ 5.24 GHz @ 18, 24, 36, 48, 54 Mbps –14.5 – –...

  • Page 87: Wlan 5 Ghz Transmitter Performance Specifications

    PRELIMINARY CYW43353 15.6 WLAN 5 GHz Transmitter Performance Specifications Note: The specifications in Table 34 include the use of the CYW43353's internal PAs and are specified at the chip port. Table 35. WLAN 5 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum...

  • Page 88: General Spurious Emissions Specifications

    PRELIMINARY CYW43353 15.7 General Spurious Emissions Specifications Table 36. General Spurious Emissions Specifications Parameter Condition/Notes Min. Typ. Max. Unit Frequency range – 2400 – 2500 General Spurious Emissions TX emissions 30 MHz < f < 1 GHz RBW = 100 kHz –...

  • Page 89: Ldo (Ldo3P3)

    PRELIMINARY CYW43353 Table 37. Core Buck Switching Regulator (CBUCK) Specifications (Cont.) Specification Notes Min. Typ. Max. Units Input supply voltage ramp-up 0 to 4.3V – – µs time The maximum continuous voltage is 4.8V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative duration over the lifetime of the device, are allowed.

  • Page 90: Ldo (Btldo2P5)

    PRELIMINARY CYW43353 16.3 2.5V LDO (BTLDO2P5) Table 39. BTLDO2P5 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage Min. = 2.5V + 0.2V = 2.7V. Dropout voltage requirement must be met under maximum load for performance specifications. Nominal output voltage Default = 2.5V.

  • Page 91: Cldo

    PRELIMINARY CYW43353 16.4 CLDO Table 40. CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement 1.35 must be met under maximum load. Output current – – Output voltage, V Programmable in 25 mV steps.

  • Page 92: Lnldo

    PRELIMINARY CYW43353 16.5 LNLDO Table 41. LNLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. = 1.2V + 0.15V = 1.35V dropout voltage requirement 1.35 must be met under maximum load. Output current – – Output voltage, V Programmable in 25 mV steps.

  • Page 93: System Power Consumption

    PRELIMINARY CYW43353 17. System Power Con sumption Note: Unless otherwise stated, these values apply for the conditions specified in Table 26, “Recommended Operating Conditions and Characteristics,”. 17.1 WLAN Current Consumption Table 42 shows the typical, total current consumed by the CYW43353. To calculate total-solution current consumption for designs using external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in Table All values in...
  • Page 94 PRELIMINARY CYW43353 Table 42. Typical WLAN Current Consumption (CYW43353 Current Only) (Cont.) VBAT = 3.6V, VDDIO = 1.8V, T 25°C Bandwidth Band Mode (MHz) (GHz) Vbat, mA , μA Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port) Transmit, CCK 5, 8 Transmit, MCS8, HT20, SGI...

  • Page 95: Bluetooth Current Consumption

    PRELIMINARY CYW43353 17.2 Bluetooth Current Consumption The Bluetooth BLE current consumption measurements are shown in Table Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table ■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. ■...

  • Page 96: Interface Timing And Ac Characteristics

    PRELIMINARY CYW43353 18. Interface Ti ming and AC Characteristics 18.1 SDIO/gSPI Timing 18.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 32 Table Figure 32. SDIO Bus Timing (Default Mode) SDIO_CLK Input Output ODLY ODLY (max)

  • Page 97: Sdio High-Speed Mode Timing

    PRELIMINARY CYW43353 18.1.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 33 Table Figure 33. SDIO Bus Timing (High-Speed Mode) 50% VDD SDIO_CLK Input Output ODLY Table 45. SDIO Bus Timing Parameters (High-Speed Mode) Parameter Symbol Minimum...

  • Page 98: Sdio Bus Timing Specifications In Sdr Modes

    PRELIMINARY CYW43353 18.1.3 SDIO Bus Timing Specifications in SDR Modes 18.1.3.1. Clock Timing Figure 34. SDIO Clock Timing (SDR Modes) SDIO_CLK Table 46. SDIO Bus Clock Timing Parameters (SDR Modes) Parameter Symbol Minimum Maximum Unit Comments – – SDR12 mode –...
  • Page 99 PRELIMINARY CYW43353 18.1.3.2. Device Input Timing Figure 35. SDIO Bus Input Timing (SDR Modes) SDIO_CLK CMD input DAT[3:0] input Table 47. SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments SDR104 Mode – = 10 pF, VCT = 0.975V CARD –...
  • Page 100 PRELIMINARY CYW43353 18.1.3.3. Device Output Timing Figure 36. SDIO Bus Output Timing (SDR Modes up to 100 MHz) SDIO_CLK ODLY CMD output DAT[3:0] output Table 48. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments –...

  • Page 101: Sdio Bus Timing Specifications In Ddr50

    PRELIMINARY CYW43353 Table 49. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit Comments Card output phase Δt –350 +1550 Delay variation due to temp change after tuning 0.60 – =2.88 ns @208 MHz Δt = +1550 ps for junction temperature of Δt = 90 degrees during operation...
  • Page 102 PRELIMINARY CYW43353 Table 50. SDIO Bus Clock Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments – – DDR50 mode – – 0.2 × tCLK < 4.00 ns (max) @50 MHz, C = 10 pF CARD Clock duty cycle –...
  • Page 103 PRELIMINARY CYW43353 Table 51. SDIO Bus Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments Input CMD Input setup time – < 10pF (1 Card) CARD Input hold time – < 10pF (1 Card) CARD Output CMD Output delay time –...

  • Page 104: Gspi Signal Timing

    PRELIMINARY CYW43353 18.1.5 gSPI Signal Timing The gSPI host and device always use the rising edge of clock to sample data. Figure 41. gSPI Timing Table 52. gSPI Timing Parameters Parameter Symbol Minimum Maximum Units Note Clock period 20.8 – = 48 MHz Clock high/low T2/T3...

  • Page 105: Power-Up Sequence And Timing

    PRELIMINARY CYW43353 19. Power-Up Sequence and Timing 19.1 Sequencing of Reset and Regulator Control Signals The CYW43353 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure Figure...
  • Page 106 PRELIMINARY CYW43353 Figure 43. WLAN = OFF, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 44. WLAN = ON, Bluetooth = OFF 32.678 kHz  Sleep Clock 90% of VH VBAT* VDDIO ~ 2 Sleep cycles WL_REG_ON 100 ms BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. 3. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high.  BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high.
  • Page 107 PRELIMINARY CYW43353 Figure 45. WLAN = OFF, Bluetooth = ON 32.678 kHz  Sleep Clock 90% of VH VBAT* VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high . Document Number: 002-14949 Rev. *G Page 106 of 113...

  • Page 108: Package Information

    PRELIMINARY CYW43353 20. Package Information 20.1 Package Thermal Characteristics Table 54. Package Thermal Characteristics Characteristic WLBGA  32.9 (°C/W) (value in still air)  2.56 (°C/W)  0.98 (°C/W)  (°C/W) 3.30  (°C/W) 9.85 Maximum Junction Temperature T (°C) Maximum Power Dissipation (W) 1.119 No heat sink, TA = 70°C.

  • Page 109: Mechanical Information

    PRELIMINARY CYW43353 21. Mechanical Info rmation Figure 46. 145-Ball WLBGA Package Mechanical Information 002-13196 Rev. *A Document Number: 002-14949 Rev. *G Page 108 of 113...
  • Page 110 PRELIMINARY CYW43353 Figure 47. WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up Note: No top-layer metal is allowed in keep-out areas. Document Number: 002-14949 Rev. *G Page 109 of 113...

  • Page 111: Ordering Information

    PRELIMINARY CYW43353 22. Ordering Information Operating Ambient Part Number Package Description Temperature CYW43353LIUBG 145 ball WLBGA (4.87 mm × 5.413 Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1 for –40°C to +85°C mm, 0.4 mm pitch) Automotive and Industrial Applications 23.

  • Page 112: Document History Page

    PRELIMINARY CYW43353 Document History Page Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and In- dustrial Applications Document Number: 002-14949 Revision Submission Date Description of Change 07/02/2013 43353-DS100-R Initial release 04/02/2014 43353-DS101-R Updated: • The cover page and the general features . •...

  • Page 113: Added Cypress Part Numbering Scheme And Mapping Table On Page

    PRELIMINARY CYW43353 Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and In- dustrial Applications Document Number: 002-14949 05/28/2014 43353-DS102-R Updated: • The Features listed in the front matter of the document. • By changing all instances of Bluetooth 4.0 to Bluetooth 4.1 throughout the document.

  • Page 114: Sales, Solutions, And Legal Information

    PRELIMINARY CYW43353 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. ® Products PSoC Solutions ®...

This manual is also suitable for:

Cypress bcm43353Cypress bcm43353liubgCypress cyw43353liubg

Table of Contents