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7.1.6.4. Long Frame Sync, Slave Mode
PCM_BCLK
PCM_SYNC
PCM_OUT
6
PCM_IN
Table 8. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Ref No.
1
PCM bit clock frequency
2
PCM bit clock LOW
3
PCM bit clock HIGH
4
PCM_SYNC setup
5
PCM_SYNC hold
6
PCM_OUT delay
7
PCM_IN setup
8
PCM_IN hold
9
Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT
becoming high impedance
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 12. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
4
5
Bit 0
Bit 1
Bit 0
Bit 1
Characteristics
2
3
9
HIGH IMPEDANCE
8
7
Minimum
Typical
–
–
41
–
41
–
8
–
8
–
0
–
8
–
8
–
0
–
CYW43353
Maximum
Unit
12
MHz
–
ns
–
ns
–
ns
–
ns
25
ns
–
ns
–
ns
25
ns
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