Infineon Cypress CYW43353 Manual page 102

Table 50. SDIO Bus Clock Timing Parameters (DDR50 Mode)
Parameter Symbol
– t
CLK
– t ,t
CR
Clock duty cycle –
18.1.4.4. Data Timing, DDR50 Mode
SDIO_CLK
DAT[3:0]
Invalid
input
DAT[3:0]
output
Document Number: 002-14949 Rev. *G
PRELIMINARY
Minimum Maximum
20 –
– 0.2 × tCLK
CF
45 55
Figure 40. SDIO Data Timing (DDR50 Mode)
t t
ISU2x IH2x
Data Invalid
t
ODLY2x
t
ODLY2x
(min)
Data
In DDR50 mode, DAT[3:0] lines are sampled on both edges of
the clock (not applicable for CMD line)
Unit
ns DDR50 mode
ns t
CR
% –
F
PP
t t
ISU2x IH2x
Data
(max)
t
ODLY2x
(min)
Data
Comments
, t < 4.00 ns (max) @50 MHz, C
CF
Invalid Data
t
(max)
ODLY2x
Available timing
window for card
Data
output transition
Available timing
window for host to
sample data from card
CYW43353
= 10 pF
CARD
Invalid
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