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5.5 Bluetooth Power Management Unit
The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through
power management registers or packet handling in the baseband core. The power management functions provided by the
CYW43353 are:
RF Power Management
■
Host Controller Power Management
■
BBC Power Management
■
5.5.1 RF Power Management
The BBC generates power-down control signals to the 2.4 GHz transceiver for the transmit path, receive path, PLL, and power
amplifier. The transceiver then processes the power-down functions accordingly.
5.5.2 Host Controller Power Management
When running in UART mode, the CYW43353 may be configured so that dedicated signals are used for power management hand-
shaking between the CYW43353 and the host. The basic power saving functions supported by those handshaking signals include
the standard Bluetooth defined power savings modes and standby modes of operation.
Table 4
describes the power-control handshake signals used with the UART interface.
Table 4. Power Control Pin Description
Signal
BT_DEV_WAKE
BT_GPIO_0
BT_HOST_WAKE
BT_GPIO_1
CLK_REQ
BT_CLK_REQ_OUT
WL_CLK_REQ_OUT
Note: Pad function Control Register is set to 0 for these pins. See
Document Number: 002-14949 Rev. *G
PRELIMINARY
Mapped to Pin
Type
I
O
O
Bluetooth device wake-up: Signal from the host to the CYW43353
indicating that the host requires attention.
•
Asserted: The Bluetooth device must wake-up or remain awake.
•
Deasserted: The Bluetooth device may sleep when sleep criteria are
met.
The polarity of this signal is software configurable and can be asserted
high or low.
Host wake up. Signal from the CYW43353 to the host indicating that the
CYW43353 requires attention.
•
Asserted: host device must wake-up or remain awake.
•
Deasserted: host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted
high or low.
The CYW43353 asserts CLK_REQ when either the Bluetooth or WLAN
block wants the host to turn on the reference clock. The CLK_REQ polarity
is active-high. Add an external 100 kΩ pull-down resistor to ensure the
signal is deasserted when the CYW43353 powers up or resets when
VDDIO is present.
DC Characteristics
for more details.
CYW43353
Description
Page 23 of 113
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