Sdio High-Speed Mode Timing - Infineon Cypress CYW43353 Manual

18.1.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of
SDIO_CLK
Input
Output
Table 45. SDIO Bus Timing
Parameter
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
Clock high time
Clock rise time
Clock fall time
Input setup time
Input hold time
Output delay time – Data Transfer Mode
Output hold time
Total system capacitance (each line)
Timing is based on CL  40pF load on CMD and Data.
1.
2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 33. SDIO Bus Timing (High-Speed Mode)
50% VDD
t
ODLY
1
Parameters (High-Speed Mode)
SDIO CLK (all values are referred to minimum VIH and maximum VIL
Inputs: CMD, DAT (referenced to CLK)
Outputs: CMD, DAT (referenced to CLK)
Figure 33 and Table 45.
f
PP
t t
WL WH
t t
THL TLH
t t
ISU IH
t
OH
Symbol Minimum
fPP 0
fOD 0
tWL 7
tWH 7
tTLH –
tTHL –
tISU 6
tIH 2
tODLY –
tOH 2.5
CL –
CYW43353
Typical Maximum
2
)
– 50
– 400
– –
– –
– 3
– 3
– –
– –
– 14
– –
– 40
Unit
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
Page 96 of 113