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Table 14. gSPI Registers (Cont.)
Address
Register
x0004
Interrupt register
x0005
Interrupt register
x0006–
Interrupt enable register
x0007
x0008–
Status register
x000B
x000C–
F1 info register
x000D
x000E–
F2 info register
x000F
x0010–
F3 info register
x0011
x0014–
Test–Read only register
x0017
x0018–
Test–R/W register
x001B
Figure 25
shows the WLAN boot-up sequence from power-up to firmware download.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Bit
Access
Default
0
R/W
0
1
R
0
2
R
0
5
R
0
6
R
0
7
R
0
5
R
0
6
R
0
7
R
0
15:
R/W/U
16'hE0E7
0
31:
R
32'h0000
0
0
R
1
1
R
0
13:
R/U
12'h40
2
0
R/U
1
1
R
0
15:
R/U
14'h800
2
0
R/U
1
1
R
0
15:
R/U
14'h800
2
31:
R
32'hFEED
0
BEAD
31:
R/W/U
32'h00000
0
000
Description
Requested data not available; Cleared by writing a 1 to this
location
F2/F3 FIFO underflow due to last read
F2/F3 FIFO overflow due to last write
F2 packet available
F3 packet available
F1 overflow due to last write
F1 Interrupt
F2 Interrupt
F3 Interrupt
Particular Interrupt is enabled if a corresponding bit is set
Same as status bit definitions
F1 enabled
F1 ready for data transfer
F1 max packet size
F2 enabled
F2 ready for data transfer
F2 max packet size
F3 enabled
F3 ready for data transfer
F3 max packet size
This register contains a predefined pattern, which the host can
read and determine if the gSPI interface is working properly.
This is a dummy register where the host can write some pattern
and read it back to determine if the gSPI interface is working
properly.
CYW43353
Page 48 of 113
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