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Table 15. WLBGA Signal Descriptions (Cont.)
WLBGA Ball#
Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific functions. See
GPIO/SDIO Alternative Signal Functions,"
B6
C6
D6
B5
C5
D5
C4
D4
H1
E5
H12
J12
B4
H3
N2
K1
L1
G2
G1
J3
H2
E6
F6
G6
F7
J6
K6
K5
H6
Document Number: 002-14949 Rev. *G
PRELIMINARY
Signal Name
WLAN GPIO Interface
for additional details.
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
JTAG_SEL
WRF_XTAL_IN
WRF_XTAL_OUT
LPO_IN
CLK_REQ
NCF
NCF
NCF
BT_PCM_CLK/BT_PCMCLK
BT_PCM_IN
BT_PCM_OUT
BT_PCM_SYNC
BT_UART_CTS_N/BT_UART_CTS
BT_UART_RTS_N/
BT_UART_RTS/BT_LED
BT_UART_RXD/ BT_RFDISABLE2
BT_UART_TXD
BT_I2S_CLK
BT_I2S_DO
BT_I2S_DI
BT_I2S_WS
Type
I/O
Programmable GPIO pins.
I/O
Note: These GPIO signals can be configured by software: as either
inputs or outputs, to have internal pull-ups or pull-downs enabled or
I/O
disabled, and to use either a high or low polarity upon assertion.
I/O
I/O
I/O
I/O
I/O
I/O
JTAG Interface
I/O
JTAG select. Pull high to select the JTAG interface. If the JTAG inter-
face is not used, this pin may be left floating or connected to ground.
Note: See
Table 21, "CYW43353 GPIO/SDIO Alternative Signal
Functions,"
for the JTAG signal pins.
Clocks
I
XTAL oscillator input.
O
XTAL oscillator output.
I
External sleep clock input (32.768 kHz).
O
Reference clock request (shared by BT and WLAN).
–
No Connect
–
No Connect
–
No Connect
Bluetooth PCM
I/O
PCM clock; can be master (output) or slave (input).
I
PCM data input.
O
PCM data output.
I/O
PCM sync; can be master (output) or slave (input).
Bluetooth UART
I
UART clear-to-send. Active-low clear-to-send signal for the HCI
UART interface.
O
UART request-to-send. Active-low request-to-send signal for the
HCI UART interface. BT LED control pin.
I
UART serial input. Serial data input for the HCI UART interface. BT
RF disable pin 2.
O
UART serial output. Serial data output for the HCI UART interface.
Bluetooth/FM I2S
I/O
2
I
S clock, can be master (output) or slave (input).
I/O
2
I
S data output.
I/O
2
I
S data input.
I/O
2
I
S WS; can be master (output) or slave (input).
CYW43353
Description
Table 21, "CYW43353
Page 58 of 113
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