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8.4 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external co-located wireless device,
such as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance.
Figure 16
shows the LTE coexistence interface. See
multiplexed signals such as the GPIO pins.
See
Table 9, "Example of Common Baud Rates,"
Figure 16. Cypress GCI or BT-SIG Mode LTE Coexistence Interface for CYW43353
8.5 UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins (see
SDIO Alternative Signal
Functions,"). Provided primarily for debugging during development, this UART enables the CYW43353 to
operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible
with the industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction.
8.6 JTAG Interface
The CYW43353 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-
ization test tools during board bringup. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
See
Table 21, "CYW43353 GPIO/SDIO Alternative Signal Functions,"
Document Number: 002-14949 Rev. *G
PRELIMINARY
Table 21, "CYW43353 GPIO/SDIO Alternative Signal Functions,"
for UART baud rates.
BCM43353
GCI
WLAN
BTFM
NOTES:
SECI_OUT/BT_TXD and SECI_IN/BT_RXD, on the BCM43353, are multiplexed on
the GPIOs.
The 2-wire LTE coexistence interface is intended for future compatibility with the BT
SIG 2-wire interface that is being standardized for Core 4.1.
ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is
achieved by setting the GPIO mask registers appropriately.
SECI_OUT/BT_TXD
SECI_IN/BT_TXD
for JTAG pin assignments.
CYW43353
LTE\IC
UART_IN
UART_OUT
Table 21, "CYW43353 GPIO/
Page 40 of 113
for details on
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