Page 1 TLE9262BQXV33 System Basis Chip Mid-Range+ System Basis Chip Family Quality Requirement Category: Automotive Features • Two integrated Low-Drop Voltage Regulators: Main regulator (5 V or 3.3 V up to 250 mA) and auxiliary regulator (5 V up to 100 mA) with off-board usage protection •...
Page 2: Table Of Contents
TLE9262BQXV33 Table of Contents Overview ............... . 6 Block Diagram .
Page 3 TLE9262BQXV33 External Components ..............55 Calculation of R .
Page 4 TLE9262BQXV33 Interrupt Function ............. . . 98 13.1...
Page 5 TLE9262BQXV33 Revision History ..............174 Data Sheet Rev.
Page 6: Overview
CAN Partial Networking variants for 5V (TLE926x-3QX) and 3.3V (TLE926x-3QXV33) output voltage Device Description The TLE9262BQXV33 is a monolithic integrated circuit in an exposed pad VQFN-48 (7mm x 7mm) power package with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).
Page 7 TLE9262BQXV33 Overview Product Features • Very low quiescent current consumption in Stop- and Sleep Mode • Periodic Cyclic Wake in SBC Normal- and Stop Mode • Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode • Low-Drop Voltage Regulator 3.3V, 250mA •...
Page 8: Block Diagram
TLE9262BQXV33 Block Diagram Block Diagram VSHS High Side VCC2 FO3/TEST Fail Safe Alternative function for FO2/3: GPIO 1/2 STATE MACHINE Interrupt Control Window Watchdog RESET GENERATOR VCAN Alternative function for WK 1/2: WAKE Voltage measurement TXDCAN REGISTER RXDCAN CAN cell...
Page 9: Pin Configuration
TLE9262BQXV33 Pin Configuration Pin Configuration Pin Assignment VCAN 37 24 WK3 GND 38 23 WK2 CANL 39 22 WK1 CANH 40 21 FO1 n.c. 41 20 GND TLE9262 LIN1 42 19 n.c. GND 43 18 VCC2 PG-VQFN-48 N.U. 44 17 VCC1 n.c.
Page 10: Pin Definitions And Functions
TLE9262BQXV33 Pin Configuration Pin Definitions and Functions Symbol Function Ground n.c. not connected; internally not bonded. VCC3REF VCC3REF; Collector connection for external PNP, reference input VCC3B VCC3B; Base connection for external PNP VCC3SH VCC3SH; Emitter connection for external PNP, shunt connection n.c.
Page 11 TLE9262BQXV33 Pin Configuration Symbol Function SPI Chip Select Not Input Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or Normal Mode and for indicating failures. Active low. During start-up used to set the SBC configuration. External pull-up sets config 1/3, no external pull-up sets config 2/4.
Page 12: Hints For Unused Pins
TLE9262BQXV33 Pin Configuration Hints for Unused Pins It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI: • WK1/2/3: connect to GND and disable WK inputs via SPI •...
Page 13: General Product Characteristics
TLE9262BQXV33 General Product Characteristics General Product Characteristics Absolute Maximum Ratings Table 1 Absolute Maximum Ratings = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note /...
Page 14 TLE9262BQXV33 General Product Characteristics Table 1 Absolute Maximum Ratings (cont’d) = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Number Test Condition Min.
Page 15: Functional Range
TLE9262BQXV33 General Product Characteristics Functional Range Table 2 Functional Range Parameter Symbol Values Unit Note / Number Test Condition Min. Typ. Max. Supply Voltage – P_4.2.1 S,func section Chapter 15.10 LIN Bus Voltage – P_4.2.2 S,LIN,func CAN Supply Voltage 4.75 –...
Page 16: Thermal Resistance
TLE9262BQXV33 General Product Characteristics Thermal Resistance Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Number Test Condition Min. Typ. Max. Junction to Soldering Point – – Exposed Pad P_4.3.1 thJSP Junction to Ambient – – P_4.3.2 thJA 1) Not subject to production test, specified by design.
Page 17: Current Consumption
TLE9262BQXV33 General Product Characteristics Current Consumption Table 4 Current Consumption Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.
Page 18 TLE9262BQXV33 General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Feature Incremental Current Consumption Current consumption for CAN –...
Page 19 TLE9262BQXV33 General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Current consumption per LIN –...
Page 20 TLE9262BQXV33 General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 2)3)6) Current consumption for HSx –...
Page 21: System Features
The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in Chapter 16.The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9262BQXV33 is compatible to other devices of the TLE926x and TLE927x families. Data Sheet Rev. 1.00...
Page 22: Block Description Of State Machine
TLE9262BQXV33 System Features Block Description of State Machine The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the current SBC mode.
Page 23: Device Configuration And Sbc Init Mode
TLE9262BQXV33 System Features 5.1.1 Device Configuration and SBC Init Mode The SBC starts up in SBC Init Mode after crossing the power-on reset threshold (see also Chapter 15.3) POR,r and the watchdog will start with a long open window During this power-on phase following configurations are stored in the device: •...
Page 24 TLE9262BQXV33 System Features POR,r VCC1 RT1,r Continuous Filtering with CFG_F Configuration selection monitoring period Figure 4 Hardware Configuration Selection Timing Diagram There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1 overvoltage behavior. The configurations can be selected via the external connection on the INT pin and the...
Page 25 TLE9262BQXV33 System Features Table 6 shows the configurations and the device behavior in case of a VCC1 overvoltage detection when VCC1_OV_RST is set: Table 6 Device Behavior in Case of VCC1 Overvoltage Detection Config INT Pin (CFGP) VCC1_O Event VCC1_...
Page 26: Sbc Init Mode
TLE9262BQXV33 System Features 5.1.1.2 SBC Init Mode In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In the SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open window the watchdog has to be triggered.
Page 27: Sbc Normal Mode
TLE9262BQXV33 System Features 5.1.2 SBC Normal Mode The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining the Fail-Safe Mode behavior).
Page 28: Sbc Stop Mode
TLE9262BQXV33 System Features 5.1.3 SBC Stop Mode The SBC Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage regulators VCC1, VCC2 and VCC3 into a low-power mode. In this mode VCC1 is still active and supplying the microcontroller, which can enter a power down mode.
Page 29: Sbc Sleep Mode
TLE9262BQXV33 System Features 5.1.4 SBC Sleep Mode The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events or for the SBC to perform autonomous actions (e.g. cyclic sense). In this mode, VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs...
Page 30: Sbc Restart Mode
TLE9262BQXV33 System Features 5.1.5 SBC Restart Mode There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the microcontroller: • in case of undervoltage on VCC1 in SBC Normal and in SBC Stop Mode,...
Page 31: Sbc Fail-Safe Mode
TLE9262BQXV33 System Features Note: An overvoltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if CFGP = ‘1’ (Config 1/3). Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.
Page 32: Sbc Development Mode
TLE9262BQXV33 System Features Table 8 Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode Prev. SBC Failure Event DEV_ TSD2 VCC1_ VCC1_ VCC1_ VCC1_ Mode STAT FAIL UV_FS Normal 1 x Watchdog Failure 01 Normal...
Page 33 TLE9262BQXV33 System Features Note: The absolute maximum ratings of the pin FO3/TEST must be observed. To increase the robustness of this pin during debugging or programming a series resistor between FO3/TEST and the connector can be added (see Figure 61).
Page 34: Wake Features
TLE9262BQXV33 System Features Wake Features Following wake sources are implemented in the device: Chapter 12 • Static Sense: WK inputs are permanently active (see • Cyclic Sense: WK inputs only active during on-time of cyclic sense period (see below) •...
Page 35: Configuration And Operation Of Cyclic Sense
TLE9262BQXV33 System Features 5.2.1.1 Configuration and Operation of Cyclic Sense The correct sequence to configure the cyclic sense is shown in Figure 6. All the configurations have to be performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”...
Page 36 TLE9262BQXV33 System Features The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of the WK input value between the first and second cycle recognized during the on-time of the second cycle will cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode.
Page 37 TLE9262BQXV33 System Features A wake event due to cyclic sense will set the respective bit WK1_WU, WK2_WU, or WK3_WU. During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC Normal or SBC Stop Mode.
Page 38: Cyclic Sense In Low Power Mode
TLE9262BQXV33 System Features Filter time High Switch Spike open closed High = WK = Low (but ignored because = High Learning = Low ≠WK change during filter time ) Cycle = WK = WK wake event = Low no wake event...
Page 39: Cyclic Wake
TLE9262BQXV33 System Features 5.2.2 Cyclic Wake The cyclic wake feature is intended to reduce the quiescent current of the device and application. For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically trigger an interrupt in SBC Normal and SBC Stop Mode.
Page 40: Internal Timer
TLE9262BQXV33 System Features 5.2.3 Internal Timer The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or to perform cyclic sense on the wake inputs. Therefore, the timers can be mapped to the dedicated HS switches by SPI (via HS_CTRL1...2).
Page 41: Voltage Regulator 1
TLE9262BQXV33 Voltage Regulator 1 Voltage Regulator 1 Block Description V CC1 Vref Overtemperature Shutdown State Machine Bandgap Reference Figure 11 Module Block Diagram Functional Features 3.3V low-drop voltage regulator • Undervoltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection •...
Page 42: Functional Description
TLE9262BQXV33 Voltage Regulator 1 Functional Description The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and in SBC Fail-Safe Mode. The regulator can provide an output current up to I...
Page 43: Electrical Characteristics
TLE9262BQXV33 Voltage Regulator 1 Electrical Characteristics Table 9 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol...
Page 44 TLE9262BQXV33 Voltage Regulator 1 1) In SBC Stop Mode, the specified output voltage tolerance applies when I has exceeded the selected active peak VCC1 threshold ( ) but with increased current consumption. VCC1,Ipeak1,r VCC1,Ipeak2,r 2) Not subject to production test, specified by design.
Page 45 TLE9262BQXV33 Voltage Regulator 1 Figure 13 Characterization results of on-resistance range of VCC1 pass device during low drop operation for I = 150mA Data Sheet Rev. 1.00 2017-07-31...
Page 46: Voltage Regulator 2
TLE9262BQXV33 Voltage Regulator 2 Voltage Regulator 2 Block Description V CC2 Vref Overtemperature State Shutdown Machine Bandgap Reference Figure 14 Module Block Diagram Functional Features • 5 V low-drop voltage regulator • Protected against short to battery voltage, e.g. for off-board sensor supply •...
Page 47: Functional Description
TLE9262BQXV33 Voltage Regulator 2 Functional Description In SBC Normal Mode VCC2 can be switched on or off via SPI. For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode.
Page 48: Electrical Characteristics
TLE9262BQXV33 Voltage Regulator 2 Electrical Characteristics Table 10 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol...
Page 49 TLE9262BQXV33 Voltage Regulator 2 Figure 15 Typical on-resistance of VCC2 pass device during low drop operation for I = 30mA Data Sheet Rev. 1.00 2017-07-31...
Page 50 TLE9262BQXV33 Voltage Regulator 2 Figure 16 On-resistance range of VCC2 pass device during low drop operation for I = 50mA Data Sheet Rev. 1.00 2017-07-31...
Page 51: External Voltage Regulator 3
TLE9262BQXV33 External Voltage Regulator 3 External Voltage Regulator 3 Block Description VCC3SH VCC3B VCC3REF CC3base CC3shunt > V shunt_threshold State Machine Figure 17 Functional Block Diagram Functional Features • Low-drop voltage regulator with external PNP transistor (up to 350mA with 470mΩ shunt resistor) •...
Page 52: Functional Description
TLE9262BQXV33 External Voltage Regulator 3 Functional Description The external voltage regulator can be used as an independent voltage regulator or in load-sharing mode with VCC1. Setting VCC3_ON in the M_S_CTRL register in SBC Normal Mode sets the stand-alone configuration of VCC3 as an independent voltage regulator.
Page 53: External Voltage Regulator As Independent Voltage Regulator
TLE9262BQXV33 External Voltage Regulator 3 when the bit VCC3_LS_ STP_ON is set and when load sharing is configured (for detailed protection features Chapter 15.7 Chapter 16.3). Table 12 External Voltage Regulator State by SBC Mode SBC Mode Load Sharing Mode...
Page 54: External Voltage Regulator In Load Sharing Mode
TLE9262BQXV33 External Voltage Regulator 3 SHUNT 100 Ω VCC3SH VCC3B VCC3REF CC3base CC3shunt > V shunt_threshold State Machine Figure 19 Protecting the VCC3 against inductive short circuits when configured as an independent voltage regulator for off-board supply 8.2.2 External Voltage Regulator in Load Sharing Mode The purpose of the load sharing mode is to increase the total current capability of VCC1 without increase of the power dissipation within the SBC.
Page 55: External Components
Figure 20 VCC3 in Load Sharing Configuration External Components Characterization is performed with the BCP52-16 from Infineon (I < 200 mA) and with MJD253. Other PNP transistors can be used. However, the functionality must be checked in the application. Figure 20 shows one hardware set up used.
Page 56: Calculation Of R
TLE9262BQXV33 External Voltage Regulator 3 Calculation of R SHUNT As a independent regulator, the maximum current I where the limit starts and the bit I > I is set is CC3max CC3max determined by the shunt resistor R and the Output Current Shunt Voltage Threshold V...
Page 57: Electrical Characteristics
TLE9262BQXV33 External Voltage Regulator 3 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all outputs open; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Page 58 TLE9262BQXV33 External Voltage Regulator 3 Table 14 Electrical Characteristics (cont’d) Values Parameter Symbol Note or Test Condition Number Min. Typ. Max. External Regulator Output 3.23 3.3V 3.37 SBC Normal Mode; P_8.6.22 CC3,out4 Voltage stand-alone (VCC3 = 3.3V) configuration 10 mA < I <...
Page 59 TLE9262BQXV33 External Voltage Regulator 3 3) At Tj > 125°C, the power transistor leakage could be increased, which has to be added to the quiescent current of the application independently if the regulator is turned on/off. To prevent an overvoltage condition at no load due to this increased leakage, an internal clamping structure will automatically turn on at typ.
Page 60 TLE9262BQXV33 External Voltage Regulator 3 Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease regulation reaction time” CCbase CC3base, 50% rlinc rldec Figure 21 Regulator Reaction Time Data Sheet Rev. 1.00 2017-07-31...
Page 61 TLE9262BQXV33 External Voltage Regulator 3 Typical Load Sharing Characteristics using the BCP52-16 PNP transistor and a 1 Ω shunt resistor 0,35 Tj = 27°C 0,30 Tj = 150°C 0,25 Tj = -40°C 0,20 0,15 0,10 0,05 - Icc3 vs. Icc1 Load Sharing Ratio - Icc1 vs.
Page 62: High-Side Switch
TLE9262BQXV33 High-Side Switch High-Side Switch Block Description VSHS HS Gate Control Overcurrent Detection Open Load (On) Figure 24 High-Side Module Block Diagram Features • Dedicated supply pin VSHS for high-side outputs • Overvoltage and undervoltage switch off - configurable via SPI •...
Page 63: Over- And Undervoltage Switch Off
TLE9262BQXV33 High-Side Switch 9.2.1 Over- and Undervoltage Switch Off All HS drivers in on-state are switched off in case of overvoltage on VSHS ). If the voltage drops below SHS,OVD the overvoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit HS_OV_SD_EN.
Page 64: Pwm And Timer Function
TLE9262BQXV33 High-Side Switch 9.2.5 PWM and Timer Function Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL, PWM2_CTRL).
Page 65: Electrical Characteristics
TLE9262BQXV33 High-Side Switch Electrical Characteristics Table 15 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol Unit...
Page 66: High Speed Can Transceiver
TLE9262BQXV33 High Speed CAN Transceiver High Speed CAN Transceiver 10.1 Block Description VCAN SPI Mode Control Driver CANH Output TXDCAN Stage Temp.- CANL timeout Protection To SPI diagnostic VCAN = 2.5V BIAS CC 1 RXDCAN Receiver Wake Receiver Figure 25 Functional Block Diagram 10.2...
Page 67 TLE9262BQXV33 High Speed CAN Transceiver The different transceiver modes can be controlled via the SPI bits. Figure 26 shows the possible transceiver mode transitions when changing the SBC mode. SBC Mode CAN Transceiver Mode SBC Stop Mode Receive Only Wake Capable...
Page 68: Can Off Mode
TLE9262BQXV33 High Speed CAN Transceiver FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking. The TLE926x- 3QX variants of this family also support the CAN FD tolerant mode. 10.2.1 CAN OFF Mode The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is intended to completely stop CAN activities or when CAN communication is not needed.
Page 69: Can Receive Only Mode
TLE9262BQXV33 High Speed CAN Transceiver 10.2.3 CAN Receive Only Mode In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This mode is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.
Page 70 TLE9262BQXV33 High Speed CAN Transceiver Entering low -power mode , when selective wake-up function is disabled Bus recessive > t or not supported WAKE1 Wait Bias off Bias off Bus dominant > t WAKE1 optional: expired WAKE2 Bias off Bus recessive > t...
Page 71 TLE9262BQXV33 High Speed CAN Transceiver Wake-Up in SBC Stop and Normal Mode In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic transition to Normal Mode.
Page 72: Txd Time-Out Feature
TLE9262BQXV33 High Speed CAN Transceiver 10.2.5 TXD Time-out Feature If the TXD signal is dominant for a time t > t , in CAN Normal Mode, the TXD time-out function TXD_CAN_TO deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being blocked permanently due to an error.
Page 73: Electrical Characteristics
TLE9262BQXV33 High Speed CAN Transceiver 10.3 Electrical Characteristics Table 17 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with...
Page 74 TLE9262BQXV33 High Speed CAN Transceiver Table 17 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
Page 75 TLE9262BQXV33 High Speed CAN Transceiver Table 17 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
Page 76 TLE9262BQXV33 High Speed CAN Transceiver Table 17 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
Page 77 TLE9262BQXV33 High Speed CAN Transceiver Table 17 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
Page 78 TLE9262BQXV33 High Speed CAN Transceiver 1) Not subject to production test, specified by design. shall be observed during dominant and recessive state and also during the transition dominant to recessive and vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2 MBit/s);...
Page 79 TLE9262BQXV33 High Speed CAN Transceiver TXDCAN 5x t Bit(TXD) Bit(TXD) Loop_f =CANH-CANL diff 900mV 500mV Bit(Bus) RXDCAN Loop_r Bit(RXD) Figure 31 From ISO 11898-2: tloop, tbit(TXD), tbit(Bus), tbit(RXD) definitions Data Sheet Rev. 1.00 2017-07-31...
Page 80: Lin Transceiver
TLE9262BQXV33 LIN Transceiver LIN Transceiver 11.1 Block Description VSHS SPI Mode Control VCC1 Driver TxD Input Temp.- Output Protection Current TXDLIN Stage Timeout Limit To SPI Diagnostic Receiver VCC1 Filter VSHS RXDLIN Wake Receiver Figure 32 Block Diagram 11.1.1 LIN Specifications The LIN network is standardized by international regulations.
Page 81: Functional Description
TLE9262BQXV33 are the interface between the micro controller and the physical LIN Bus. The digital output data from the micro controller are driven to the LIN bus via the TXD input pin on the TLE9262BQXV33. The transmit data stream on the TXD input is converted to a LIN bus signal with optimized slew rate to minimize the EME level of the LIN network.
Page 82: Lin Normal Mode
TLE9262BQXV33 LIN Transceiver 11.2.2 LIN Normal Mode The LIN Transceiver is enabled via SPI in SBC Normal Mode. LIN Normal Mode is designed for normal data transmission/reception within the LIN network. The Mode is available in SBC Normal Mode and in SBC Stop Mode.
Page 83: Lin Wake Capable Mode
TLE9262BQXV33 LIN Transceiver 11.2.4 LIN Wake Capable Mode This mode can be used in SBC Stop, Sleep, Restart and Normal Mode by programming via SPI and it is used to monitor bus activities. It is automatically accessed in SBC Fail-Safe Mode. A wake up is detected, if a recessive...
Page 84: Txd Time-Out Feature
In case the supply voltage is dropping below the VSHS undervoltage detection threshold (VSHS < V ), the SHS,UVD TLE9262BQXV33 disables the output and receiver stages. If the power supply reaches a higher level than the undervoltage detection threshold (VSHS > V ), the TLE9262BQXV33 continues with normal operation.
Page 85: Slope Selection
TLE9262BQXV33 LIN Transceiver 11.2.8 Slope Selection The LIN transceiver offers a LIN Low-Slope Mode for 10.4 kBaud communication and a LIN Normal-Slope Mode for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low-Slope Mode, transmitter uses a lower slew rate to further reduce the EME compared to Normal-Slope Mode.
Page 86: Electrical Characteristics
TLE9262BQXV33 LIN Transceiver 11.3 Electrical Characteristics Table 19 Electrical Characteristics = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Page 87 TLE9262BQXV33 LIN Transceiver Table 19 Electrical Characteristics (cont’d) = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values...
Page 88 TLE9262BQXV33 LIN Transceiver Table 19 Electrical Characteristics (cont’d) = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values...
Page 89 TLE9262BQXV33 LIN Transceiver VSHS 100 nF Figure 36 Simplified Test Circuit for Dynamic Characteristics Data Sheet Rev. 1.00 2017-07-31...
Page 90 TLE9262BQXV33 LIN Transceiver (input to transmitting node ) Bus _dom (max ) Bus_rec (min ) Thresholds of Rec (max) receiving node 1 Dom (max) (Transceiver supply of transmitting Thresholds of node ) Rec(min ) receiving node 2 Dom(min ) Bus _dom (min )
Page 91: Wake And Voltage Monitoring Inputs
TLE9262BQXV33 Wake and Voltage Monitoring Inputs Wake and Voltage Monitoring Inputs 12.1 Block Description Internal Supply PU_WK PD_WK Logic MONx_Input_Circuit_ext.vsd Figure 38 Wake Input Block Diagram Features • Three High-Voltage inputs with a 3V (typ.) threshold voltage • Alternate Measurement function for high-voltage sensing via WK1 and WK2 •...
Page 92: Functional Description
TLE9262BQXV33 Wake and Voltage Monitoring Inputs 12.2 Functional Description The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep and SBC Fail-Safe Mode.
Page 93: Wake Input Configuration
TLE9262BQXV33 Wake and Voltage Monitoring Inputs 12.2.1 Wake Input Configuration To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure integrated current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes (including the filter time) can be configured via the SPI register WK_FLT_CTRL.
Page 94 TLE9262BQXV33 Wake and Voltage Monitoring Inputs Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to be assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1...
Page 95: Alternate Measurement Function With Wk1 And Wk2
TLE9262BQXV33 Wake and Voltage Monitoring Inputs 12.2.2 Alternate Measurement Function with WK1 and WK2 12.2.2.1 Block Description This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the protected WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage compensation for LED lighting by changing the duty cycle of the High-Side outputs.
Page 96: Electrical Characteristics
TLE9262BQXV33 Wake and Voltage Monitoring Inputs Note: There is a diode in series to the switch S1 (not shown in the Figure 60), which will influence the temperature behavior of the switch. 12.3 Electrical Characteristics Table 23 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C;...
Page 97 TLE9262BQXV33 Wake and Voltage Monitoring Inputs 1100 VS = 13.5V 1000 500 μA 250 μA 100 μA 50 μA JUNCTION TEMPERATURE (°C) Figure 41 Typical Drop Voltage Characteristics of S1 (between WK1 & WK2) Data Sheet Rev. 1.00 2017-07-31...
Page 98: Interrupt Function
TLE9262BQXV33 Interrupt Function Interrupt Function 13.1 Block and Functional Description Time Interrupt logic Figure 42 Interrupt Block Diagram The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 42.
Page 99 TLE9262BQXV33 Interrupt Function INTD Update of Update of WK_STAT register WK_STAT register optional Read & Clear WK_STAT no WK no WK contents No SPI Read & Clear Read & Clear Command sent WK_STAT WK1 + WK2 no WK contents Interrupt_Behavior .vsd...
Page 100: Electrical Characteristics
TLE9262BQXV33 Interrupt Function 13.2 Electrical Characteristics Table 24 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Page 101: Fail Outputs
TLE9262BQXV33 Fail Outputs Fail Outputs 14.1 Block and Functional Description 5V_int SBC Init Mode test TEST FO1/2 Failure logic FO3/TEST FO_PL Failure Logic Figure 44 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low signalization.
Page 102: General Purpose I/O Functionality Of Fo2 And Fo3 As Alternate Function
TLE9262BQXV33 Fail Outputs Note: The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the 1st watchdog failure if selected for Config2. The three fail outputs are activated simultaneously with following output functionalities: FO1: Static fail output •...
Page 103 TLE9262BQXV33 Fail Outputs Table 25 Fail-Output and GPIO configuration behavior during the respective SBC Modes SBC Normal SBC Stop Mode SBC Sleep Mode SBC Restart SBC Fail-Safe Configuration Mode Mode Mode FOx (default) fixed fixed active / fixed active configurable...
Page 104: Electrical Characteristics
TLE9262BQXV33 Fail Outputs 14.2 Electrical Characteristics Table 26 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Page 105 TLE9262BQXV33 Fail Outputs 1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS 2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC Development Mode and SBC User Mode operation.
Page 106: Supervision Functions
TLE9262BQXV33 Supervision Functions Supervision Functions 15.1 Reset Function Reset logic Incl. filter & delay Figure 46 Reset Block Diagram 15.1.1 Reset Output Description The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold V .
Page 107: Soft Reset Description
TLE9262BQXV33 Supervision Functions t < t The reset threshold can be configured via SPI in SBC Normal Mode , default is V undervoltage Init Trigger Trigger Init = long open window = closed window = open window SBC Init SBC Normal...
Page 108: Watchdog Function
TLE9262BQXV33 Supervision Functions 15.2 Watchdog Function The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the microcontroller stops serving the watchdog due to a lock up in the software. Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN: •...
Page 109: Time-Out Watchdog
TLE9262BQXV33 Supervision Functions Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows: • In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the watchdog WD_FAIL...
Page 110: Window Watchdog
TLE9262BQXV33 Supervision Functions 15.2.2 Window Watchdog Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer period is divided between an closed and an open window. The watchdog must be triggered within the open window.
Page 111: Watchdog Setting Check Sum
TLE9262BQXV33 Supervision Functions 15.2.3 Watchdog Setting Check Sum A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting. The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (15.1)).
Page 112: Watchdog During Sbc Stop Mode
TLE9262BQXV33 Supervision Functions 15.2.4 Watchdog during SBC Stop Mode The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in Figure 50.
Page 113: Watchdog Start In Sbc Stop Mode Due To Bus Wake
TLE9262BQXV33 Supervision Functions 15.2.5 Watchdog Start in SBC Stop Mode due to Bus Wake In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog with any BUS wake (CAN or LIN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS (= default value after POR).
Page 114: Vs Power On Reset
TLE9262BQXV33 Supervision Functions 15.3 VS Power On Reset At power up of the device, the VS Power on Reset is detected when VS > and the SPI bit is set to POR,r indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be...
Page 115: Undervoltage Vs And Vshs
TLE9262BQXV33 Supervision Functions 15.4 Undervoltage VS and VSHS If the supply voltage VS reaches the undervoltage threshold then the SBC does the following measures: S,UV VS_UV • SPI bit is set. No other error bits are set. The bit can be cleared once the condition is not present anymore, Chapter 8.2...
Page 116: Vcc1 Overvoltage
TLE9262BQXV33 Supervision Functions VCC1 SBC Normal SBC Restart SBC Normal Figure 52 VCC1 Undervoltage Timing Diagram An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high dynamic loads on VCC1: • A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset threshold), •...
Page 117: Vcc1 Short Circuit And Vcc3 Diagnostics
TLE9262BQXV33 Supervision Functions that external noise could be coupled into the VCC1 supply line. Especially, in case the VCC1 output current in SBC STOP Mode is below the active peak threshold (I VCC1,Ipeak VCC1 CC1,OV VCC1,OV_F SBC Normal SBC Restart...
Page 118: Thermal Protection
TLE9262BQXV33 Supervision Functions 15.9 Thermal Protection Three independent and different thermal protection features are implemented in the SBC according to the system impact: • Individual thermal shutdown of specific blocks • Temperature prewarning of main microcontroller supply VCC1 • SBC thermal shutdown due to VCC1 overtemperature 15.9.1...
Page 119: Temperature Prewarning
TLE9262BQXV33 Supervision Functions 15.9.2 Temperature Prewarning As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches the thermal prewarning temperature threshold . Then the status bit is set. This bit can only be cleared via SPI once the overtemperature is not present anymore.
Page 120: Electrical Characteristics
TLE9262BQXV33 Supervision Functions 15.10 Electrical Characteristics Table 28 Electrical Specification = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Page 121 TLE9262BQXV33 Supervision Functions Table 28 Electrical Specification (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Values...
Page 122 TLE9262BQXV33 Supervision Functions Table 28 Electrical Specification (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Values...
Page 123 TLE9262BQXV33 Supervision Functions Table 28 Electrical Specification (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Values...
Page 124: Serial Peripheral Interface
TLE9262BQXV33 Serial Peripheral Interface Serial Peripheral Interface 16.1 SPI Block Description The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 54).
Page 125: Failure Signalization In The Spi Data Output
TLE9262BQXV33 Serial Peripheral Interface 16.2 Failure Signalization in the SPI Data Output When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI commands are either invalid SBC mode commands or commands which are prohibited by the state machine to avoid undesired device or system states (see below).
Page 126 TLE9262BQXV33 Serial Peripheral Interface Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not valid if the CLK is high on a falling edge of CSN...
Page 127: Spi Programming
SPI Programming For the TLE9262BQXV33, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual configuration and status information, 8 data bits (BIT15...8) are used.
Page 128 TLE9262BQXV33 Serial Peripheral Interface 10 11 12 13 Address Bits Data Bits Register content of selected address 10 11 12 13 Status Information Field Data Bits time LSB is sent first in SPI message Figure 55 SPI Operation Mode Data Sheet Rev.
Page 129: Spi Bit Mapping
TLE9262BQXV33 Serial Peripheral Interface 16.4 SPI Bit Mapping The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’).
Page 130 TLE9262BQXV33 Serial Peripheral Interface 15 14 13 12 11 10 7 Address Bits [bits 0...6] 8 Data Bits [bits 8...15] Reg. Type for Register Selection for Configuration & Status Information M_S_CTRL 0 0 0 0 0 0 1 HW_CTRL 0 0 0...
Page 131 TLE9262BQXV33 Serial Peripheral Interface Figure 57 TLE9262BQXV33 SPI Bit Mapping Data Sheet Rev. 1.00 2017-07-31...
Page 132: Spi Control Registers
TLE9262BQXV33 Serial Peripheral Interface 16.5 SPI Control Registers READ/WRITE Operation (see also Chapter 16.3): • The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset. • The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.
Page 133: General Control Registers
TLE9262BQXV33 Serial Peripheral Interface 16.5.1 General Control Registers M_S_CTRL Mode- and Supply Control (Address 000 0001 POR / Soft Reset Value: 0000 0000 Restart Value: 00x0 00xx VCC1_OV_RS MODE_1 MODE_0 VCC3_ON VCC2_ON_1 VCC2_ON_0 VCC1_RT_1 VCC1_RT_0 Field Bits Type Description MODE...
Page 134 TLE9262BQXV33 Serial Peripheral Interface HW_CTRL Mode- and Supply Control (Address 000 0010 POR / Soft Reset Value: y000 y000 Restart Value: xx0x x00x SOFT_RESET VCC3_VS_UV VCC3_LS_ST VCC3_V_CFG FO_ON VCC3_LS Reserved _OFF P_ON Field Bits Type Description VCC3_ VCC3 Output Voltage Configuration (if configured as...
Page 135 TLE9262BQXV33 Serial Peripheral Interface If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered and the FOx outputs will be disabled. See also Chapter 14 for FOx activation and deactivation.
Page 136 TLE9262BQXV33 Serial Peripheral Interface WD_CTRL Watchdog Control (Address 000 0011 POR / Soft Reset Value: 0001 0100 Restart Value: x0xx 0100 WD_STM_ WD_EN_ CHECKSUM WD_WIN Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0 EN_0 WK_BUS Field Bits Type Description CHECKSUM 7 Watchdog Setting Check Sum Bit...
Page 137 TLE9262BQXV33 Serial Peripheral Interface BUS_CTRL_1 Bus Control (Address 000 0100 POR / Soft Reset Value: 0010 0000 Restart Value: xxxy y0yy LIN_FLASH LIN_LSM LIN_TXD_TO LIN1_1 LIN1_0 Reserved CAN_1 CAN_0 Field Bits Type Description LIN_FLASH LINx Flash Programming Mode , Slope control mechanism active...
Page 138 TLE9262BQXV33 Serial Peripheral Interface BUS_CTRL_2 Bus Control (Address 000 0101 POR / Soft Reset Value: 0000 0000 ; Restart Value: 00x0 0000 Reserved Reserved I_PEAK_TH Reserved Reserved Reserved Reserved Reserved Field Bits Type Description Reserved Reserved, always reads as 0...
Page 139 TLE9262BQXV33 Serial Peripheral Interface WK_CTRL_1 Internal Wake Input Control (Address 000 0110 POR / Soft Reset Value: 0000 0000 Restart Value: xx00 0000 TIMER2_WK_ TIMER1_WK_ WD_STM_ Reserved Reserved Reserved Reserved Reserved EN_1 Field Bits Type Description TIMER2_WK Timer2 Wake Source Control (for cyclic wake)
Page 140 TLE9262BQXV33 Serial Peripheral Interface WK_CTRL_2 External Wake Source Control (Address 000 0111 POR / Soft Reset Value: 0000 0111 Restart Value: x0x0 0xxx INT_GLOBAL Reserved WK_MEAS Reserved Reserved WK3_EN WK2_EN WK1_EN Field Bits Type Description INT_ Global Interrupt Configuration (see also Chapter 13.1)
Page 141 TLE9262BQXV33 Serial Peripheral Interface WK_PUPD_CTRL Wake Input Level Control (Address 000 1000 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx xxxx Reserved Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0 Field Bits Type Description Reserved Reserved, always reads as 0...
Page 142 TLE9262BQXV33 Serial Peripheral Interface WK_FLT_CTRL Wake Input Filter Time Control (Address 000 1001 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx xxxx Reserved Reserved WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0 Field Bits Type Description Reserved Reserved, always reads as 0...
Page 143 TLE9262BQXV33 Serial Peripheral Interface TIMER1_CTRL Timer1 Control and Selection (Address 000 1100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 TIMER1_ TIMER1_ TIMER1_ TIMER1_ TIMER1_ TIMER1_ Reserved Reserved ON_2 ON_1 ON_0 PER_2 PER_1 PER_0 Field Bits Type...
Page 144 TLE9262BQXV33 Serial Peripheral Interface TIMER2_CTRL Timer2 Control and selection (Address 000 1101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 TIMER2_ TIMER2_ TIMER2_ TIMER2_ TIMER2_ TIMER2_ Reserved Reserved ON_2 ON_1 ON_0 PER_2 PER_1 PER_0 Field Bits Type...
Page 145 TLE9262BQXV33 Serial Peripheral Interface SW_SD_CTRL Switch Shutdown Control (Address 001 0000 POR / Soft Reset Value: 0000 0000 Restart Value: 0xxx 0000 HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R Reserved Reserved Reserved Reserved Reserved Field Bits Type Description Reserved Reserved, always reads as 0 HS_OV_SD_ Shutdown Disabling of HS1...4 in case of VSHS OV...
Page 146 TLE9262BQXV33 Serial Peripheral Interface HS_CTRL1 High-Side Switch Control 1 (Address 001 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 Reserved HS2_2 HS2_1 HS2_0 Reserved HS1_2 HS1_1 HS1_0 Field Bits Type Description Reserved Reserved, always reads as 0...
Page 147 TLE9262BQXV33 Serial Peripheral Interface HS_CTRL2 High-Side Switch Control 2 (Address 001 0101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 Reserved HS4_2 HS4_1 HS4_0 Reserved HS3_2 HS3_1 HS3_0 Field Bits Type Description Reserved Reserved, always reads as 0...
Page 148 TLE9262BQXV33 Serial Peripheral Interface GPIO_CTRL GPIO Configuration Control (Address 001 0111 POR / Soft Reset Value: 0000 0000 Restart Value: xxxx xxxx FO_DC_1 FO_DC_0 GPIO2_2 GPIO2_1 GPIO2_0 GPIO1_2 GPIO1_1 GPIO1_0 Field Bits Type Description FO_DC Duty Cycle Configuration of FO3 (if selected)
Page 149 TLE9262BQXV33 Serial Peripheral Interface PWM1_CTRL PWM1 Configuration Control (Address 001 1000 POR / Soft Reset Value: 0000 0000 Restart Value: xxxx xxxx PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0 Field Bits Type Description PWM1_DC PWM1 Duty Cycle (bit0=LSB; bit7=MSB)
Page 150 TLE9262BQXV33 Serial Peripheral Interface PWM_FREQ_CTRL PWM Frequency Configuration Control (Address 001 1100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0x0x Reserved Reserved Reserved Reserved Reserved PWM2_FREQ Reserved PWM1_FREQ Field Bits Type Description Reserved Reserved, always reads as 0...
Page 151: Spi Status Information Registers
TLE9262BQXV33 Serial Peripheral Interface 16.6 SPI Status Information Registers READ/CLEAR Operation (see also Chapter 16.3): • One 16-bit SPI command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to...
Page 152: General Status Registers
TLE9262BQXV33 Serial Peripheral Interface 16.6.1 General Status Registers SUP_STAT_2 Supply Voltage Fail Status (Address 100 0000 POR / Soft Reset Value: 0000 0000 Restart Value: 0x0x xxxx Reserved VS_UV Reserved VCC3_OC VCC3_UV VCC3_OT VCC1_OV VCC1_WARN Field Bits Type Description Reserved...
Page 153 TLE9262BQXV33 Serial Peripheral Interface SUP_STAT_1 Supply Voltage Fail Status (Address 100 0001 POR / Soft Reset Value: y000 0000 Restart Value: xxxx xx0x VSHS_UV VSHS_OV VCC2_OT VCC2_UV VCC1_SC VCC1_UV_FS VCC1_UV Field Bits Type Description Power-On Reset Detection , No POR...
Page 154 TLE9262BQXV33 Serial Peripheral Interface THERM_STAT Thermal Protection Status (Address 100 0010 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0xxx Reserved Reserved Reserved Reserved Reserved TSD2 TSD1 Field Bits Type Description Reserved Reserved, always reads as 0 TSD2...
Page 155 TLE9262BQXV33 Serial Peripheral Interface DEV_STAT Device Information Status (Address 100 0011 POR / Soft Reset Value: 0000 0000 Restart Value: xx00 xxxx DEV_STAT_1 DEV_STAT_0 Reserved Reserved WD_FAIL_1 WD_FAIL_0 SPI_FAIL FAILURE Field Bits Type Description DEV_STAT Device Status before Restart Mode 00B , Cleared (Register must be actively cleared) 01B , Restart due to failure (WD fail, TSD2, VCC1_UV);...
Page 156 TLE9262BQXV33 Serial Peripheral Interface BUS_STAT_1 Bus Communication Status (Address 100 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0xx0 0xxx Reserved LIN1_FAIL_1 LIN1_FAIL_0 Reserved Reserved CAN_FAIL_1 CAN_FAIL_0 VCAN_UV Field Bits Type Description Reserved Reserved, always reads as 0...
Page 157 TLE9262BQXV33 Serial Peripheral Interface WK_STAT_1 Wake-up Source and Information Status (Address 100 0110 POR / Soft Reset Value: 0000 0000 Restart Value: 0xxx 0xxx Reserved LIN1_WU CAN_WU TIMER_WU Reserved WK3_WU WK2_WU WK1_WU Field Bits Type Description Reserved Reserved, always reads as 0...
Page 158 TLE9262BQXV33 Serial Peripheral Interface WK_STAT_2 Wake-up Source and Information Status (Address 100 0111 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx 0000 Reserved Reserved GPIO2_WU GPIO1_WU Reserved Reserved Reserved Reserved Field Bits Type Description Reserved Reserved, always reads as 0...
Page 159 TLE9262BQXV33 Serial Peripheral Interface WK_LVL_STAT WK Input Level (Address 100 1000 POR / Soft Reset Value: xx00 0xxx Restart Value: xxxx 0xxx SBC_DEV CFGP GPIO2_LVL GPIO1_LVL Reserved WK3_LVL WK2_LVL WK1_LVL _LVL Field Bits Type Description SBC_DEV Status of SBC Operating Mode at FO3/TEST Pin...
Page 160 TLE9262BQXV33 Serial Peripheral Interface HS_OC_OT_STAT High-Side Switch Overload Status (Address 101 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 xxxx Reserved Reserved Reserved Reserved HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT Field Bits Type Description Reserved Reserved, always reads as 0 HS4_OC_OT 3 Overcurrent &...
Page 161 TLE9262BQXV33 Serial Peripheral Interface HS_OL_STAT High-Side Switch Open-Load Status (Address 101 0101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 xxxx Reserved Reserved Reserved Reserved HS4_OL HS3_OL HS2_OL HS1_OL Field Bits Type Description Reserved Reserved, always reads as 0...
Page 162: Family And Product Information Register
TLE9262BQXV33 Serial Peripheral Interface 16.6.2 Family and Product Information Register FAM_PROD_STAT Family and Product Identification Register (Address 111 1110 POR / Soft Reset Value: 0011 yyyy Restart Value: 0011 yyyy FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 Field Bits...
Page 163: Electrical Characteristics
TLE9262BQXV33 Serial Peripheral Interface 16.7 Electrical Characteristics Table 30 Electrical Characteristics = 5.5 V to 28 V, T = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol...
Page 164 TLE9262BQXV33 Serial Peripheral Interface Table 30 Electrical Characteristics (cont’d) = 5.5 V to 28 V, T = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit...
Page 165: Application Information
TLE9262BQXV33 Application Information Application Information 17.1 Application Diagram Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Page 166 TLE9262BQXV33 Application Information Note: Unused outputs are recommended to be left unconnected on the application board. If unused output pins are routed to an external connector which leaves the ECU, then these pins should have provision for a zero ohm jumper (depopulated if unused) or ESD protection.
Page 167 Active Components e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are not needed, then connect VSHS to VS pins As required by application, configure series resistor accordingly As required by application, configure series resistor accordingly e.g.
Page 168 TLE9262BQXV33 Application Information VBAT VBAT e.g. 470uF VCC1 µC TxD LIN1 TxD LIN1 RxD LIN1 RxD LIN1 LOGIC State Machine TxD CAN TxD CAN RxD CAN RxD CAN Reset TLE9262 ADC_x Vbat_uC max. 500uA ≥10k ISO Pulse ≥10n protection Note: Vbat_uC Max.
Page 169 TLE9262BQXV33 Application Information 5V_int SBC Init Mode test TEST Connector FO3/ /Jumper TEST FO_PL Failure Logic Figure 61 Hint for Increasing the Robustness of pin FO3/TEST during Debugging or Programming Data Sheet Rev. 1.00 2017-07-31...
Page 170: Esd Tests
TLE9262BQXV33 Application Information 17.2 ESD Tests Note: Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) has been performed. The results and test conditions are available in a test report. The target values for the test are listed Table 32 below.
Page 171: Thermal Behavior Of Package
TLE9262BQXV33 Application Information 17.3 Thermal Behavior of Package Below figure shows the thermal resistance (R ) of the device vs. the cooling area on the bottom of the PCB th_JA for Ta = 85°C. Every line reflects a different PCB and thermal via design.
Page 172 TLE9262BQXV33 Application Information Cross Section (JEDEC 2s2p) with Cooling Area Cross Section (JEDEC 1s0p) with Cooling Area 70µm modelled (traces) 35µm, 90% metalization* 35µm, 90% metalization* 70µm / 5% metalization + cooling area *: means percentual Cu metalization on each layer...
Page 173: Package Outlines
The tie bars have an internal connection to the exposed pad. For assembly recommendations please also refer to the documents "Recommendations for Board Assembly (VQFN and IQFN)" and "VQFN48 Layout Hints" on the Infineon website (www.infineon.com). The PG-VQFN-48-31 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to support Automatic Optical Inspection (AOI).
Page 174 TLE9262BQXV33 Revision History Revision History Revision Date Changes Rev. 1.00 2017-07-31 Initial Release Data Sheet Rev. 1.00 2017-07-31...
Page 175 Infineon Technologies, customer's products and any use of the product of Infineon Technologies’ products may not be used in Infineon Technologies in customer's applications. any applications where a failure of the product or any...
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