Gspi Signal Timing; Jtag Timing - Infineon Cypress CYW43353 Manual

18.1.5 gSPI Signal Timing

The gSPI host and device always use the rising edge of clock to sample data.
Table 52. gSPI Timing Parameters
Parameter Symbol
Clock period T1
Clock high/low T2/T3
T4/T5
1
Clock rise/fall time
Input setup time T6
Input hold time T7
Output setup time T8
Output hold time T9
–
2
CSX to clock
–
a
Clock to CSX
1. Limit applies when SPI_CLK = F
setup and hold time limits are complied with.
2. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-word transaction).

18.2 JTAG Timing

Table 53. JTAG Timing Characteristics
Signal Name
TCK
TDI
TMS
TDO
JTAG_TRST
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 41. gSPI Timing
Minimum
20.8 –
(0.45 × T1) – T4 (0.55 × T1) – T4
– 2.5
5.0 –
5.0 –
5.0 –
5.0 –
7.86 –
– –
. For slower clock speeds, longer rise/fall times are acceptable provided that the transitions are monotonic and the
max
Output
Period Maximum
125 ns –
– –
– –
– 100 ns
250 ns –
Maximum Units
ns F
ns –
ns Measured from 10% to 90% of VDDIO
ns Setup time, SIMO valid to SPI_CLK active edge
ns Hold time, SPI_CLK active edge to SIMO invalid
ns Setup time, SOMI valid before SPI_CLK rising
ns Hold time, SPI_CLK active edge to SOMI invalid
ns CSX fall to 1st rising edge
ns Last falling edge to CSX high
Output
Minimum
–
–
–
0 ns
–
CYW43353
Note
= 48 MHz
max
Setup Hold
– –
20 ns 0 ns
20 ns 0 ns
– –
– –
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