Generic Spi Mode - Infineon Cypress CYW43353 Manual

Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD
line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper
programming of the SDIO host's internal pull-ups

9.2 Generic SPI Mode

In addition to the full SDIO mode, the CYW43353 includes the option of using the simplified generic SPI (gSPI) interface/protocol.
Characteristics of the gSPI mode include:
Supports up to 48 MHz operation
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Supports fixed delays for responses and data from device
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Supports alignment to host gSPI frames (16 or 32 bits)
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Supports up to 2 KB frame size per transfer
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Supports little endian (default) and big endian configurations
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Supports configurable active edge for shifting
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Supports packet transfer through DMA for WLAN
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gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1].
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 18. Signal Connections to SDIO Host (SD 1-Bit Mode)
SD Host
Figure 19. Signal Connections to SDIO Host (gSPI Mode)
SD Host
CLK
CMD
DATA
CYW43353
IRQ
RW
SCLK
DI
DO
CYW43353
IRQ
CS
CYW43353
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