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PRELIMINARY
CYW43353
6. Microprocessor and Memory Unit for Bluetooth
®
™
The Bluetooth microprocessor core is based on the ARM
Cortex-M3
32-bit RISC processor with embedded ICE-RT debug and
JTAG interface units. It runs software from the link control (LC) layer, up to the host controller interface (HCI).
The ARM core is paired with a memory unit that contains 608 KB of ROM memory for program storage and boot ROM, 192 KB of
RAM for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset to enable the same
device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches
may be downloaded from the host to the CYW43353 through the UART transports.
6.1 RAM, ROM, and Patch Memory
The CYW43353 Bluetooth core has 192 KB of internal RAM which is mapped between general purpose scratch-pad memory and
patch memory and 608 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory
capability enables feature additions and bug fixes to the ROM memory.
6.2 Reset
The CYW43353 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset
(POR) circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.
Document Number: 002-14949 Rev. *G
Page 27 of 113
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