Pcm Interface Timing - Infineon Cypress CYW43353 Manual

7.1.6 PCM Interface Timing

7.1.6.1. Short Frame Sync, Master Mode
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM_IN
Table 5. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No.
1 PCM bit clock frequency
2 PCM bit clock LOW
3 PCM bit clock HIGH
4 PCM_SYNC delay
5 PCM_OUT delay
6 PCM_IN setup
7 PCM_IN hold
8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT
becoming high impedance
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure 9. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
4
5
Characteristics
2
3
8
HIGH IMPEDANCE
6
Minimum Typical
– –
41 –
41 –
0 –
0 –
8 –
8 –
0 –
CYW43353
7
Maximum Unit
12 MHz
– ns
– ns
25 ns
25 ns
– ns
– ns
25 ns
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