Power-Up Sequence And Timing; Sequencing Of Reset And Regulator Control Signals; Description Of Control Signals; Control Signal Timing Diagrams - Infineon Cypress CYW43353 Manual

19. Power-Up Sequence and Timing

19.1 Sequencing of Reset and Regulator Control Signals

The CYW43353 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and
internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of
the signals for various operational states (see
minimum required values; longer delays are also acceptable.

19.1.1 Description of Control Signals

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the
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internal CYW43353 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW43353 regulators. If both the
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BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT
section is in reset.
Note:
For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles
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(where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed,
then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.
The CYW43353 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after
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VDDC and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiat-
ing SDIO accesses.
VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO
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should NOT be present first or be held high before VBAT is high.
Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high. BT_REG_ON can be driven low
100 ms after WL_REG_ON goes high

19.1.2 Control Signal Timing Diagrams

32.678 kHz
Sleep Clock
VBAT*
VDDIO
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high
before VBAT is high.
Document Number: 002-14949 Rev. *G
PRELIMINARY
Figure
Figure 42. WLAN = ON, Bluetooth = ON
90% of VH
~ 2 Sleep cycles
42, Figure 43, and Figure 44 and Figure 45). The timing values indicated are
CYW43353
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